FPGA DIO Clock Capabilities
- Updated2023-10-23
- 1 minute(s) read
FPGA DIO Clock Capabilities
The light blue FPGA Clock Optimized designations in the RMC connector pinout indicate either SRCC or MRCC FPGA pins.
- Single-region clock capable (SRCC)—These pins provide a direct connection to the global clock distribution buffers in the FPGA. The pins also connect to the regional buffers on a specific bank of pins.
- Multi-region clock capable (MRCC)—These pins provide a direct connection to the global clock distribution buffers in the FPGA. The pins also connect to the regional and multi-regional buffers on a specific bank of pins.
Tip FPGA DIO pins through the RMC
may be used to import or export clocks. Use the CLIP generation wizard to configure DIO
lines for this capability. NI recommends that you use FPGA Clock Optimized pins when you
import a clock into LabVIEW FPGA.