Accessing User-Defined FPGA

Use one of the following methods to access the user-defined FPGA signals in LabVIEW:
  • Right-click your FPGA Target and select New » RIO Mezzanine Card... to choose a generic Digital RMC and access all 96 DIO lines with digital I/O nodes.
    Note This methodology does not allow you to configure the DIO lines as RS-232 and RS-485 processor peripherals.
    1. Right click your FPGA Target and select Launch sbRIO CLIP Generator... to launch the NI Single-Board RIO CLIP Generator application, which you can use to create a socketed component-level IP (CLIP) that defines the FPGA signals or processor peripherals to use in your application.
    2. After you create a CLIP, return to LabVIEW and right-click an RMC Socket under the FPGA Target and select Properties.
    3. In the Socket Properties dialog box, select your CLIP and click OK. The I/O appears under the socket, or the I/O is connected directly to the RT processor.
Note For a given FPGA target, you must use either the digital I/O method or the socketed CLIP method for all 96 DIO lines.