User-Defined FPGA Signals

Example applications include, but are not limited to, singled-ended or LVDS differential DAC and ADC interfaces, SPI or I2C connections to sensors, buttons, and relays. In addition to FPGA Digital I/O (DIO), you can use these pins to implement RS-232 and RS-485 devices:

DIO[47..0] and DIO[96..48] can be configured for either 2.5 V or 3.3 V. A voltage of 2.5 V allows for either 2.5 V single-ended I/O standards or differential LVDS I/O standards. A voltage of 3.3 V allows for 3.3 V single-ended I/O standards. When configuring the I/O through the CLIP both 2.5 V and 3.3 V is supported. When configuring the I/O by selecting New » RIO Mezzanine Card the voltage is fixed at 3.3 V.