PXIe-8523 Specifications

PXIe-8523 Specifications

These specifications apply to the PXIe-8523.

Revision History

Version Date changed Description
378123C-01 August 2025 Added the Ethernet PHY chipset model.
378123B-01 April 2024 Formatting updates. No specifications changed.
378123A-01 December 2019 Initial release.

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Definitions

Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

  • Typical—describes the performance met by a majority of models.
  • Nominal—describes an attribute that is based on design, conformance testing, or supplemental testing.

    • Specifications are Typical unless otherwise noted.

    Conditions

    Specifications are valid under the following conditions unless otherwise noted.

    • 0 °C to 55 °C
    Notice The terminals or pins of this device are not protected from electromagnetic interference. As a result, this device may experience reduced measurement accuracy or other temporary performance degradation when connected cables are routed in an environment with radiated or conducted radio frequency electromagnetic interference.

    PXIe-8523 Pinout

    Figure 1. PXIe-8523 Connector Pinout

    Connector Pinout

    Table 1. Signal Descriptions
    Pin Number Signal Type Signal Direction Signal Description Signal Required
    1 TRX_P Bi-directional Transceiver plus Required
    2 TRX_M Bi-directional Transceiver minus Required
    3 Shield — Shield Optional

    Physical Characteristics

    Table 2. Physical Characteristics
    Dimensions (not including connectors) 16 cm x 10 cm (6.0 in. x 3.9 in.) 3U CompactPCI slot
    Weight 200 g (7.1 oz)
    Ports 4, 100/1000BASE-T1
    I/O connectors Weidmuller BLF 3.50, 3-position
    LED indicators

    1 Link/Activity LED for each port.

    1 Status LED for each port.
    Table 3. Spring Terminal Wiring
    Wire gauge 0.14 mm2 (26 AWG) to 1.5 mm2 (16 AWG)
    Wire strip length 8 mm (0.3 in.) of insulation stripped from the end
    Ferrules 0.14 mm2 (26 AWG) to 1.5 mm2 (16 AWG), 8 mm barrel length
    Table 4. Connector Securement
    Securement type Screw flanges provided
    Torque for screw flanges 0.2 N · m to 0.25 N · m (1.8 lb · in. to 2.2 lb · in.)
    Table 5. Ethernet PHY Chipset Model
    Chipset BCM89881
    Note Refer to the PXIe-8522/8523 User Manual for additional information about I/O connectors and ferrules (included).

    Network Interface

    Table 6. Network Interface
    Port configuration 2 Taps or 4 endpoints
    Tap latency
    • 100 Mbps: 2 µs, typical
    • 1 Gbps: 5.55 µs, typical
    Protocols
    • IEEE 802.3 Raw Ethernet
    • TCP/IP
    • UDP/IP
    • AVB (IEEE 802.1Qav, AVTP)
    • IEEE 802.1AS
    Note For information about using Taps and endpoints, refer to the PXIe-8522/8523 User Manual.

    Bus Interface

    Table 7. Bus Interface
    Form factor Gen 2 x4 PXI Express, specification rev 1.0 compliant
    Slot compatibility x1[1]1 Limited performance due to PCIe bandwidth., x4, x8 and x16 PXI Express or PXI Express hybrid slots

    Power Requirements

    Table 8. Power Requirements
    Voltage (V) Current (A)
    +3.3 V DC

    2.7 A, maximum

    2.2 A, typical
    +12 V DC

    1.5 A, maximum

    1.0 A, typical

    Timing and Synchronization

    Table 9. Network Timekeeping
    Timing and synchronization protocol 802.1AS
    Network synchronization accuracy
    • 100BASE-T1: <1 µs
    • 1000BASE-T1: < µs
    Table 10. Timebases
    Local 100 MHz, shared by all ports, disciplined by PXI_Clk10 if available
    Network x4 125 MHz, 1 per port, independently disciplined by an external grand master (port is configured as a slave)[2]2 If the port is not connected to an 802.1AS network, the network timebase falls back to local time. or the local timebase (port is configured as a master)
    Table 11. Trigger I/O source
    Trigger I/O source PXI_Trig <0:7>
    Table 12. Input Trigger Capability
    Timestamps[3]3 Each timestamp can be triggered by any PXI_Trig <0:7>. x4 timestamps, one per port; each captures both local time and network time[4]4 If no external network is available, use local time instead.
    Table 13. OutputTrigger Capability
    Time triggers x4 time triggers, one per port; generated from local time or network time
    Clocks
    • x4 1 MHz, one per port; 50% duty cycle; each disciplined by network time.
    • x4 1 Hz PPS (pulse per second), one per port; 50% duty cycle; each disciplined by network time.
    Note You can export clock outputs and time triggers on any PXI_Trig<0:7>.

    Environmental Guidelines

    Notice This product is intended for use in indoor applications only.

    Environmental Characteristics

    Table 14. Temperature
    Operating0 °C to 55 °C
    Storage-40 °C to 71 °C
    Table 15. Humidity
    Operating10% to 90%, noncondensing
    Storage5% to 95%, noncondensing
    Table 16. Pollution Degree
    Pollution degree2
    Table 17. Maximum Altitude
    Maximum altitude2,000 m (800 mbar) at 25 °C ambient temperature
    Table 18. Shock and Vibration
    Operating vibration 5 Hz to 500 Hz, 0.3 g RMS
    Non-operating vibration 5 Hz to 500 Hz, 2.4 g RMS
    Operating shock30 g, half-sine, 11 ms pulse

    1 Limited performance due to PCIe bandwidth.

    2 If the port is not connected to an 802.1AS network, the network timebase falls back to local time.

    3 Each timestamp can be triggered by any PXI_Trig <0:7>.

    4 If no external network is available, use local time instead.