PXIe-8290 Specifications
- Updated2025-10-23
- 5 minute(s) read
PXIe-8290 Specifications
These specifications apply to the PXIe-8290.
Revision History
| Version | Date changed | Description |
|---|---|---|
| 379214A-01 | July 2025 | Initial release. |
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Definitions
Warranted Specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.
Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
Values are Typical unless otherwise noted.
Conditions
Specifications are valid when operating the product within the limits defined in Environmental Characteristics.
PXIe-8290 Pinout
Use the pinout to connect to terminals on the PXIe-8290.
| Connector Identifier | Connector Type | Description |
|---|---|---|
| 0–7 | Mini-SAS zHD | High-density ports used for high-speed serial communication, typically with Aurora or other HSS protocols. |
| PORT 1 | QSFP28, SFF-8679 compliant | QSFP28 ports provide four lanes of high-speed Ethernet connectivity. |
| PORT 2 |
| Pin | Symbol | Description |
|---|---|---|
| A1 | RESERVED | Reserved |
| A2 | RESERVED | Reserved |
| A3 | GND | Ground |
| A4 | Rx+ 1 | Receive Data + Lane 1 |
| A5 | Rx- 1 | Receive Data - Lane 1 |
| A6 | GND | Ground |
| A7 | Rx+ 3 | Receive Data + Lane 3 |
| A8 | Rx- 3 | Receive Data - Lane 3 |
| A9 | GND | Ground |
| B1 | RESERVED | Reserved |
| B2 | GPIO | General Purpose I/O |
| B3 | GND | Ground |
| B4 | Rx+ 0 | Receive Data + Lane 0 |
| B5 | Rx- 0 | Receive Data - Lane 0 |
| B6 | GND | Ground |
| B7 | Rx+ 2 | Receive Data + Lane 2 |
| B8 | Rx- 2 | Receive Data - Lane 2 |
| B9 | GND | Ground |
| C1 | SCL | I²C Clock |
| C2 | SDA | I²C Data |
| C3 | GND | Ground |
| C4 | Tx+ 1 | Transmit Data + Lane 1 |
| C5 | Tx- 1 | Transmit Data - Lane 1 |
| C6 | GND | Ground |
| C7 | Tx+ 3 | Transmit Data + Lane 3 |
| C8 | Tx- 3 | Transmit Data - Lane 3 |
| C9 | GND | Ground |
| D1 | RESERVED | Reserved |
| D2 | EEPROM | EEPROM Interface |
| D3 | GND | Ground |
| D4 | Tx+ 0 | Transmit Data + Lane 0 |
| D5 | Tx- 0 | Transmit Data - Lane 0 |
| D6 | GND | Ground |
| D7 | Tx+ 2 | Transmit Data + Lane 2 |
| D8 | Tx- 2 | Transmit Data - Lane 2 |
| D9 | GND | Ground |
| Pin | Symbol | Description |
|---|---|---|
| 1 | GND | Ground |
| 2 | Tx2n | Transmitter Inverted Data Input |
| 3 | Tx2p | Transmitter Non-Inverted Data Input |
| 4 | GND | Ground |
| 5 | Tx4n | Transmitter Inverted Data Input |
| 6 | Tx4p | Transmitter Non-Inverted Data Input |
| 7 | GND | Ground |
| 8 | ModSelL | Module Select |
| 9 | ResetL | Module Reset |
| 10 | Vcc Rx | +3.3V Power Supply Receiver |
| 11 | SCL | 2-Wire Serial Interface Clock |
| 12 | SDA | 2-Wire Serial Interface Data |
| 13 | GND | Ground |
| 14 | Rx3p | Receiver Non-Inverted Data Output |
| 15 | Rx3n | Receiver Inverted Data Output |
| 16 | GND | Ground |
| 17 | Rx1p | Receiver Non-Inverted Data Output |
| 18 | Rx1n | Receiver Inverted Data Output |
| 19 | GND | Ground |
| 20 | GND | Ground |
| 21 | Rx2n | Receiver Inverted Data Output |
| 22 | Rx2p | Receiver Non-Inverted Data Output |
| 23 | GND | Ground |
| 24 | Rx4n | Receiver Inverted Data Output |
| 25 | Rx4p | Receiver Non-Inverted Data Output |
| 26 | GND | Ground |
| 27 | ModPrsL | Module Present |
| 28 | IntL | Interrupt |
| 29 | Vcc Tx | +3.3V Power Supply Transmitter |
| 30 | Vcc1 | +3.3V Power Supply |
| 31 | LPMode | Low Power Mode |
| 32 | GND | Ground |
| 33 | Tx3p | Transmitter Non-Inverted Data Input |
| 34 | Tx3n | Transmitter Inverted Data Input |
| 35 | GND | Ground |
| 36 | Tx1p | Transmitter Non-Inverted Data Input |
| 37 | Tx1n | Transmitter Inverted Data Input |
| 38 | GND | Ground |
Physical Characteristics
| Dimensions | 3U, two-slot, PXI Express/Compact PCI Express module 21.6 cm × 4.1 cm × 13.0 cm (8.5 in. × 1.6 in. × 5.1 in.)
For more information, visit ni.com/dimensions and search by module number. |
| Weight | 924 g (32.59 oz) |
Communication Characteristics
| Ethernet connectivity | Port type | QSFP28 port based on Mellanox OCP card |
| Port quantity | 2 | |
| Data rate supported per port | Up to 100 GbE | |
| PXI Express link configuration | Gen3 x8 PCI Express connection | |
| Maximum Total Data Throughput | 20 GB/s | |
Reconfigurable FPGA
The PXIe-8290 provides an XCVP1202 FPGA with characteristics shown in the following table.
| Parameter | Value |
|---|---|
| System Logic Cells | 1,969 K |
| DSP slices (27 × 18 multiplier) | 3,984 |
| Embedded Block RAM | 264.0 Mb |
| Timebase reference sources | PXI Express 100 MHz (PXIe_CLK100) |
| Data transfers | DMA, programmed I/O, multi-gigabit transceivers |
| Number of DMA channels | 60 |
Onboard DRAM
| Parameter | Value |
|---|---|
| Memory size | 32 GB (4 banks of 8 GB) |
| DRAM clock rate | 1600 MHz/1850 MHz |
| Physical bus width | 64 bit |
| LabVIEW FPGA DRAM clock rate | 250 MHz |
| LabVIEW FPGA DRAM bus width | 512 bits per bank |
Bus Interface
Form factor | PCI Express Gen-3 x8 |
Power Requirements
The PXIe-8290 draws current from a combination of the 3.3 V and 12 V power rails. The maximum current drawn from each of these rails can vary depending on the cable connected to the module.
The PXIe-8290 does not supply power to connected cables directly. The power values listed reflect the module’s own power consumption when operating with different cable types. For AOCs, power is supplied by the integrated NIC component within the PXIe-8290. The NIC supports up to 5 W per QSFP port to power AOCs.
| Power Source | Voltage | Current Rating |
|---|---|---|
| PXIe Bus | 3.3 V DC | 3.5 A |
| 12 V DC | 12 A |
The total power consumption of the module is 155 W.
Environmental Guidelines
Environmental Characteristics
| Operating | 0 °C to 55 °C |
| Storage | -40 °C to 71 °C |
| Operating | 10% RH to 90% RH, noncondensing |
| Storage | 5% RH to 95% RH, noncondensing |
| Pollution degree | 2 |
| Maximum altitude | 2,000 m |
| Operating vibration | 5 Hz to 500 Hz, 0.3 g RMS |
| Non-operating vibration | 5 Hz to 500 Hz, 2.4 g RMS |
| Operating shock | 30 g, half-sine, 11 ms pulse |