PXIe-6672 Specifications

PXIe-6672 Specifications

Definitions

Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

  • Typical specifications describe the performance met by a majority of models.
  • Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.

Specifications are Characteristics unless otherwise noted.

PXIe-6672 Specifications Conditions

Specifications are valid for the range 0 °C to 55 °C unless otherwise noted.

PXIe-6672 Pinout



  1. Access LED
  2. Active LED
  3. CLKOUT Connector
  4. CLKIN Connector
  5. PFI<0..5> Connectors

CLKIN Characteristics

CLKIN fundamental frequency range[1]1 CLKIN fundamental frequency can be any multiple of 1 MHz within the range specified when the PLL is engaged and PXI_CLK10 is locking to it. The frequency must be 10 MHz when replacing PXI_CLK10 without the PLL.

1 MHz to 105 MHz, sine or square wave

Input impedance

50 Ω, nominal

Input coupling

AC

Voltage range

DC

±20 V

AC

400 mV p-p to 5 Vp-p

Absolute maximum input voltage[2]2 Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods of time can affect device reliability. Functional operation of the device outside the conditions indicated in the operational parts of the specification is not implied.

±26 V, max

CLKIN to PXI_CLK10_IN delay without PLL

14 ns to 14.7 ns, typical

CLKIN to PXI_CLK10 delay with PLL

±1 ns, max

CLKIN frequency accuracy requirement

For PLL and TCXO

±5.0 ppm

For replacing PXI_CLK10 (no PLL)

±100 ppm [3]3 This is a requirement of the PXI specification.

Jitter added to CLKIN

Without PLL

0.5 ps rms, 10 Hz to 100 kHz, typical

With PLL

0.6 ps rms, 10 Hz to 100 kHz, typical

Duty cycle distortion of CLKIN to PXI_CLK10_IN without PLL

±1%, max

Required input duty cycle when using PLL

45 to 55%

CLKOUT Characteristics

Output frequency

From PXI_CLK10

10 MHz

From TCXO

10 MHz

From DDS

1 MHz [4]4 The lower limit is load dependent because of the AC coupling. This limit is less than 1 MHz for high-impedance loads. to 105 MHz

Duty cycle

43 to 55%[5]5 The duty cycle specification covers both DDS range and TCXO.

Output impedance

50 Ω, nominal

Output coupling

AC

Table 1. Amplitude with an Open Load, software configurable to two voltage levels (low and high drive)
Open Load Square Wave
Low Drive 2.0 V p-p, typical
High Drive 5.0 V p-p, typical
Table 2. Amplitude with a 50 Ω Load, software configurable to two voltage levels (low and high drive)
50 Ω Load Square Wave
Low Drive 1.0 V p-p, typical
High Drive 2.5 V p-p, typical
Square wave rise/fall time (10 to 90%)

High or Low drive[6]6 This specification was tested at 25 ºC and with nominal power supplies.

0.5 ns to 2.5 ns

PFI <0..5>

Input Characteristics

Frequency range

DC to 105 MHz

Input impedance

50 Ω, nominal, or 1 kΩ ±10%, || 35 pF, software-selectable

Input coupling

DC

Voltage level

0 to 5 V

Absolute maximum input voltage[7]7 Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods of time can affect device reliability. Functional operation of the device outside the conditions indicated in the operational parts of the specifications is not implied.

±5.25 V, max

Input threshold

Voltage level

0 to 4.3 V, software-selectable

Voltage resolution

16.8 mV (8 bits)

Error

±40 mV

Hysteresis

50 mV

Asynchronous delay, tpd

PFI <0..5> to PXI_TRIG <0..7> output

19 to 26 ns, typical

PFI <0..5> to PXI_STAR <0..16> output

10 to 19 ns, typical

Synchronized trigger input setup time, tsetup[8]8 Relative to PXI_CLK10 at the backplane connector. When PLL is used to route CLKIN to PXI_CLK10_IN, CLKIN and PXI_CLK10 are phase locked with ±1 ns max phase difference.

16.5 ns, typical

Synchronized trigger input hold time, thold[9]9 Relative to PXI_CLK10 at the backplane connector. When PLL is used to route CLKIN to PXI_CLK10_IN, CLKIN and PXI_CLK10 are phase locked with ±1 ns max phase difference.

-9.9 ns, typical

Output Characteristics

Frequency range

DC to 105 MHz

Output impedance

50 Ω, nominal

Output coupling

DC

Voltage level

0 to 1.6 V into 50 Ω; 0 to 3.3 V into open circuit, typical

Absolute maximum applied voltage[10]10 Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods of time can affect device reliability. Functional operation of the device outside the conditions indicated in the operational parts of the specifications is not implied.

±5.25 V, max

PXI_CLK10 synchronized trigger clock to out time, tCtoQ[11]11 Relative to PXI_CLK10 at backplane connector.

10.7 ns, typical

Output-to-output skew, synchronous

500 ps, typical

PXI_STAR Trigger Characteristics

PXI_STAR <0..16> to PXI_STAR <0..16> output skew at NI PXIe-6672 backplane connector

300 ps [12]12 This specification applies to all synchronous routes to the PXI_Star lines, as well as asynchronous routes from the PFI inputs to the PXI_Star lines., typical

Asynchronous delays, tpd

PXI_STAR <0..16> to PFI <0..5> output

13 to 17 ns, typical

PXI_STAR <0..16> to PXI_TRIG <0..7> output

18 to 24 ns, typical

PXI Trigger Characteristics

PXI_TRIG <0..7> to PXI_TRIG <0..7> output skew at NI PXIe-6672 backplane connector

5 ns, typical

Asynchronous delay, ttd

PXI_TRIG <0..7> to PFI <0..5> output

15 to 22 ns, typical

TCXO Characteristics

Nominal frequency

10 MHz

Accuracy within 1 year of calibration adjustment within 0 ºC to 55 ºC operating temperature range

±3.5 ppm

Long-term stability[13]13 Includes stability of TCXO and supporting circuitry.

±1 ppm/year

Stability vs. temperature operating range (0 to 55 °C)[14]14 Includes temperature stability of TCXO and supporting circuitry.

<1.6 ppm peak-to-peak

Recommended calibration interval

1 year

DDS Characteristics

Frequency range

1 Hz to 105 MHz

Frequency resolution

< 0.075 Hz

Frequency accuracy

Equivalent to PXI_CLK10 accuracy[15]15 The DDS frequency inherits the relative frequency of PXI_CLK10. For example, if you route the TCXO to PXI_CLK10, the DDS output inherits the same relative frequency accuracy as the TCXO output.

Physical

Chassis requirement

One 3U PXI Express slot (system timing slot)

Front panel connectors

SMB male, 50 Ω

Front panel indicators

Two tricolor LEDs (green, red, and amber)

Weight

0.459 lb (208 g)

Power Requirements

Caution You can impair the protection provided by the PXIe-6672 if you use it in a manner not described in this document.

+3.3 V

2.54 A, max

+12 V

2.25 A, max

Environmental

Maximum altitude

2,000 m (800 mbar) (at 25 °C ambient temperature)

Pollution Degree

2

Indoor use only.

Operating Environment

Ambient temperature range

0 to 55 °C (Tested in accordance with IEC-60068-2-1 and IEC-60068-2-2. Meets MIL-PRF-28800F Class 3 low temperature limit and MIL-PRF-28800F Class 2 high temperature limit.)

Relative humidity range

10% to 90%, noncondensing (Tested in accordance with IEC-60068-2-56.)

Storage Environment

Ambient temperature range

-40 to 71 °C (Tested in accordance with IEC-60068-2-1 and IEC-60068-2-2. Meets MIL-PRF-28800F Class 3 limits.)

Relative humidity range

5% to 95%, noncondensing (Tested in accordance with IEC-60068-2-56.)

Shock and Vibration

Operating Shock

30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC-60068-2-27. Meets MIL-PRF-28800F Class 2 limits.)

Random Vibration

Operating

5 to 500 Hz, 0.3 grms

Nonoperating

5 to 500 Hz, 2.4 grms (Tested in accordance with IEC-60068-2-64. Nonoperating test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

Safety Compliance Standards

This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

  • IEC 61010-1, EN 61010-1
  • UL 61010-1, CSA C22.2 No. 61010-1
Note For safety certifications, refer to the product label or the Product Certifications and Declarations section.

EMC Standards

This product meets the requirements of the following EMC standards for sensitive electrical equipment for measurement, control, and laboratory use:

  • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
  • EN 55011 (CISPR 11): Group 1, Class A emissions
  • AS/NZS CISPR 11: Group 1, Class A emissions
  • FCC 47 CFR Part 15B: Class A emissions
  • ICES-001: Class A emissions
Note In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia and New Zealand (per CISPR 11) Class A equipment is intended for use only in heavy-industrial locations.
Note Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.
Note For EMC declarations and certifications, and additional information, refer to the Product Certifications and Declarations section.

CE Compliance

This product meets the essential requirements of applicable European Directives, as follows:

  • 2014/35/EU; Low-Voltage Directive (safety)
  • 2014/30/EU; Electromagnetic Compatibility Directive (EMC)

Product Certifications and Declarations

Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit ni.com/product-certifications, search by model number, and click the appropriate link.

Environmental Management

NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

For additional environmental information, refer to the Engineering a Healthy Planet web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

EU and UK Customers

  • Waste Electrical and Electronic Equipment (WEEE)—At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.

    • 电子信息产品污染控制管理办法（中国RoHS）

  • 中国RoHS— NI符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于NI中国RoHS合规性信息，请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

    • 1 CLKIN fundamental frequency can be any multiple of 1 MHz within the range specified when the PLL is engaged and PXI_CLK10 is locking to it. The frequency must be 10 MHz when replacing PXI_CLK10 without the PLL.

    2 Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods of time can affect device reliability. Functional operation of the device outside the conditions indicated in the operational parts of the specification is not implied.

    3 This is a requirement of the PXI specification.

    4 The lower limit is load dependent because of the AC coupling. This limit is less than 1 MHz for high-impedance loads.

    5 The duty cycle specification covers both DDS range and TCXO.

    6 This specification was tested at 25 ºC and with nominal power supplies.

    7 Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods of time can affect device reliability. Functional operation of the device outside the conditions indicated in the operational parts of the specifications is not implied.

    8 Relative to PXI_CLK10 at the backplane connector. When PLL is used to route CLKIN to PXI_CLK10_IN, CLKIN and PXI_CLK10 are phase locked with ±1 ns max phase difference.

    9 Relative to PXI_CLK10 at the backplane connector. When PLL is used to route CLKIN to PXI_CLK10_IN, CLKIN and PXI_CLK10 are phase locked with ±1 ns max phase difference.

    10 Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods of time can affect device reliability. Functional operation of the device outside the conditions indicated in the operational parts of the specifications is not implied.

    11 Relative to PXI_CLK10 at backplane connector.

    12 This specification applies to all synchronous routes to the PXI_Star lines, as well as asynchronous routes from the PFI inputs to the PXI_Star lines.

    13 Includes stability of TCXO and supporting circuitry.

    14 Includes temperature stability of TCXO and supporting circuitry.

    15 The DDS frequency inherits the relative frequency of PXI_CLK10. For example, if you route the TCXO to PXI_CLK10, the DDS output inherits the same relative frequency accuracy as the TCXO output.