Getting Started Guide

FlexRIO Documentation and Resources

Use the following resources to find more information about the PXIe-6569.

All documentation can be found at ni.com/manuals or in LabVIEW by clicking Help.

Table 1. FlexRIO Documentation and Resources
Document	Contents
PXIe-6569 Getting Started Guide (this document)	Installation instructions Basic programming information
PXIe-6569 Specifications	Operating environment requirements DIO specifications Clocking specifications Physical and mechanical specifications
PXIe-6569 Safety, Environmental, and Regulatory Information	Safety and compliance information Environmental information
LabVIEW FPGA Module Help	Basic functionality of the FPGA module Instructions for developing and debugging custom hardware logic
FlexRIO 21.7 Readme	Minimum system requirements Supported Application Development Environments (ADEs) Known issues and bug fixes Recent updates
FlexRIO Help	FlexRIO driver API and programming information I/O Component Level IP (CLIP) development information
LabVIEW Examples	Examples showing how to run FPGA VIs on your device Examples showing how to run host VIs on your device

Unpacking the Kit

Notice To prevent electrostatic discharge (ESD) from damaging the module, ground yourself using a grounding strap or by holding a grounded object, such as your computer chassis.

Touch the antistatic package to a metal part of the computer chassis.
Remove the module from the package and inspect it for loose components or other signs of damage.

Notice Never touch the exposed pins of connectors.

Note Do not install a module if it appears damaged in any way.
Unpack any other items and documentation from the kit.

Store the module in the antistatic package when the module is not in use.

What You Need to Get Started

Kit Contents

Verify that the following items are included in the PXIe-6569 kit.

PXIe-6569 hardware
Documentation
- PXIe-6569 Getting Started Guide (this document)
- PXIe-6569 Safety, Environmental, and Regulatory Information

Recommended Cables

NI offers two lengths of optional SEARAY™ to SEARAY cables for connecting to the pins on the front panel. The following table shows the details for each.


Model Name	Part Number
SR240M-SR240M Cable, LVDS with SE, 0.5m	787317-0R5
SR240M-SR240M Cable, LVDS with SE, 1.0m	787317-01

Installing the Software

You must be an Administrator to install NI software on your computer.

Install an ADE, such as LabVIEW or LabWindows™/CVI™.
Download the driver software installer from ni.com/downloads.
NI Package Manager downloads with the driver software to handle the installation. Refer to the NI Package Manager Manual for more information about installing, removing, and upgrading NI software using NI Package Manager.
Follow the instructions in the installation prompts.

Note Windows users may see access and security messages during installation. Accept the prompts to complete the installation.
When the installer completes, select Restart in the dialog box that prompts you to restart, shut down, or restart later.

Installing FlexRIO Modules

This section contains general installation instructions for installing a FlexRIO module in a PXI Express chassis. Refer to your chassis user manual for specific instructions and warnings. To install a module, complete the following steps:

Connect the AC power source to the PXI Express chassis before installing the module. The AC power cord grounds the chassis and protects it from electrical damage while you install the module.
Ensure that the chassis is powered off.
Install a module into a chassis slot by first placing the module card PCB into the front of the card guides (top and bottom), as shown in the following figure. Slide the module to the rear of the chassis, making sure that the injector/ejector handle is pushed down, as shown in the following figure.
When you begin to feel resistance, push up on the injector/ejector handle to fully seat the module into the chassis frame. Secure the module front panel to the chassis using the module front-panel mounting screws.
Figure 1. Installing PXI Express Modules
1. Injector/Ejector Handle
2. FlexRIO Module
3. Front Panel Mounting Screws (2x)
4. PXI Express Chassis
5. Injector/Ejector Rail

PXIe-6569 Front Panel and Connectors

The following figure shows the front panel and pin layout of the Digital Data & Control (DDC) connector on the PXIe-6569.

1378 — Figure 2. PXIe-6569 Front Panel Layout

The following figures show the pinout of the DDC connector on the PXIe-6569 for each connector type. Clock-capable pins are denoted in bold.

Signal Descriptions

The following table describes the signal connections for the PXIe-6569.


Connector Name	Signal Type	Description
DO <0...63>+/-	Data	Positive and negative differential terminals for digital output channels 0 through 63.
DI <0...63>+/-	Data	Positive and negative differential terminals for digital input channels 0 through 63.
PFI <0,1>+/-	Control	Positive and negative differential terminals for bidirectional PFI channels 0 and 1.
SE <0...7>	Data	Terminals for bidirectional single-ended channels 0 through 7.
SE_GND_TERM	Termination	Terminals that provide coupling to the single-ended channels. These signals should be terminated for the best single-ended signal integrity. These are terminated on the PXIe-6569 with 56 Ω to ground. NI recommends that these also be terminated on the user side of the SEARAY cable through a 56 Ω (±10%) resistor to GND. If the user-side termination is not possible, leave it disconnected.
CLKIN+/-, CLKOUT+/-	Clock	Terminals for clocking inputs and outputs.
GND	Ground	Ground reference for signals.
RSVD	Reserved	These pins are reserved and use of them is not supported by NI. Leave these terminals disconnected.

Verifying the Installation in MAX

Use Measurement & Automation Explorer (MAX) to configure your NI hardware. MAX informs other programs about which NI hardware products are in the system and how they are configured. MAX is automatically installed with FlexRIO.

Launch MAX.
In the configuration tree, expand Devices and Interfaces to see the list of installed NI hardware.
Installed modules appear under the name of their associated chassis.
Expand your Chassis tree item.
MAX lists all modules installed in the chassis. Your default names may vary.
Note Device Manager identifies the PXIe-6569 as the "NI FlexRIO Module (BT - KU035)" or "NI FlexRIO Module (BT - KU060)".
Note If you do not see your module listed, press <F5> to refresh the list of installed modules. If the module is still not listed, power off the system, ensure the module is correctly installed, and restart.
Record the identifier MAX assigns to the hardware. Use this identifier when programming the PXIe-6569.
Self-test the hardware by selecting the item in the configuration tree and clicking Self-Test in the MAX toolbar.
MAX self-test performs a basic verification of hardware resources.

Accessing FlexRIO with Integrated I/O Examples

The FlexRIO driver includes several example applications for LabVIEW. These examples serve as interactive tools, programming models, and as building blocks in your own applications. To access all FlexRIO with Integrated I/O getting started examples, complete the following steps.

In LabVIEW, click Help » Find Examples.
In the NI Example Finder window that opens, click Hardware Input and Output » FlexRIO » Integrated IO » Getting Started.
Double click Getting Started with FlexRIO Integrated IO.vi.

The FlexRIO with Integrated IO Project Creator window opens.
Select the example that corresponds to the name of your FlexRIO module. The Description window includes a short description of the getting started example for your device. Rename the project, select a location for the project, and click OK.
The Project Explorer window for your new project opens.

Online examples are also available to demonstrate FlexRIO basics, such as using DRAM, acquiring data, and performing high throughput streaming. To access these examples, search FlexRIO examples in the Search the community field at ni.com/examples.

PXIe-6569 Examples

Examples specific to PXIe-6569 can be found in the FlexRIO with Integrated IO Project Creator.

NI provides two getting started examples for each LVDS and FPGA configuration of the PXIe-6569: a basic interface and a SERDES interface. The following file names and descriptions demonstrate how the examples would be displayed to a user whose module includes a 32 LVDS In, 32 LVDS Out variation and a KU035 FPGA:

PXIe-6569 (32 In 32 Out - KU035) - Basic Interface.vi demonstrates device configuration and generation/acquisition of digital data using a one sample per cycle interface.
PXIe-6569 (32 In 32 Out - KU035) - SerDes Interface.vi demonstrates device configuration and generation/acquisition of digital data using an eight sample per cycle interface.

Common FlexRIO with Integrated I/O Examples

In addition to the examples within the FlexRIO with Integrated IO Project Creator, NI provides several examples that apply to all FlexRIO with Integrated I/O modules to help you perform common tasks.

The following table lists FlexRIO examples you can run from NI Example Finder:


NI Example Finder FlexRIO Example	Description
Show All FlexRIO with Integrated IO Hardware.vi	Queries and displays a set of hardware properties from all FlexRIO with Integrated I/O devices in a chassis.
Vivado Export Getting Started Ultrascale.lvproj	Demonstrates how to export your LabVIEW FPGA project into Vivado in order to develop your FPGA design in the Vivado ADE.
Read-Write Calibration Data.vi	Demonstrates how to read and write calibration data and metadata into the storage space of FlexRIO with Integrated I/O devices.

FPGA Carrier Block Diagram

PXIe-6569 I/O Block Diagram

Component-Level Intellectual Property (CLIP)

The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.

User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI.
Socketed CLIP provides the same IP integration of the user-defined CLIP, but it also allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface.

The PXIe-6569 ships with socketed CLIP items that add module I/O to the LabVIEW project.

Refer to Configuring Your Adapter Module Using LabVIEW FPGA in FlexRIO documentation for more information about CLIP.

PXIe-6569 CLIP

PXIe-6569 ships with two socketed CLIP options. These socketed CLIP options can be used as-is or can be edited to suit your application.

Refer to the following table for more information about each socketed CLIP's function and the signals used in each.

Note Both PXIe-6569 CLIP items allow individual clock output inversion.

Table 2. PXIe-6569 Socketed CLIP Items
CLIP Name	Description
PXIe-6569 Basic CLIP	Provides read/write access to all low-voltage differential signal (LVDS) and single-ended channels. You can access the LVDS data and direction lines using a U64 or U32 data type in which each bit position corresponds to an individual channel. You can access the LVDS PFI lines using a boolean data type and the single-ended PFI lines using another boolean data type. Generation channels are clocked by a single generation clock signal, and acquisition channels are clocked by a single acquisition clock signal.
PXIe-6569 SERDES Channel CLIP	Provides read/write access to all LVDS and single-ended channels using a channel-based interface. You can access the LVDS data using a U8 data type and the PFI channels using a boolean data type. Each LVDS line is connected to an OSERDES or ISERDES block that serializes or deserializes, respectively, the signal by a factor of eight by default. During acquisition or generation, the PXIe-6569 reads or writes eight bits of data per channel to or from the IDELAY or ODELAY blocks, which allow for per-channel data delay up to 1.25 ns. All OSERDES and ISERDES blocks are set to double data rate (DDR) mode.

Socketed CLIP Signals

Each LVDS configuration variant of the PXIe-6569 has a different set of signals you must use in the socketed CLIP. Some CLIP signals and data types are specific to the module variant being used. The following table lists the term used in the CLIP signals to represent each associated module variant.


LVDS Configuration Reference in CLIP	PXIe-6569 Variant
Half-In, Half-Out (HIHO)	32 LVDS In, 32 LVDS Out
All In	64 LVDS In
All Out	64 LVDS Out

Refer to Front Panel and Connectors for PXIe-6569 connector signals and the associated FPGA signal information.

PXIe-6569 Basic Socketed CLIP Signals


CLIP Signal Name	Direction	Data Type	Description
IO Ready	From CLIP	Boolean	Indicates successful configuration of the IO module with the current clocking mode settings.
IO Error	From CLIP	I32	Returns IO module errors, to be reported by the driver.
SE_Data_Output_Enable	To CLIP	Boolean	Provides read/write access to all single-ended channels. SE_Data_Output_Enable values: 1—Use SE_Data_Wr to write to the SE data line. 0—Use SE_Data_Rd to read the SE data line value.
SE_Data_Rd	From CLIP	Boolean
SE_Data_Wr	To CLIP	Boolean
LVDS_PFI_Output_Enable	To CLIP	Boolean	Provides read/write access to all low-voltage differential signal (LVDS) PFI channels. LVDS_PFI_Output_Enable values: 1—Use LVDS_PFI_Wr to write to the PFI data line. 0—Use LVDS_PFI_Rd to read the PFI data line value.
LVDS_PFI_Rd	From CLIP	Boolean
LVDS_PFI_Wr	To CLIP	Boolean
LVDS_Data_Wr	To CLIP	U32 (HIHO); U64 (All Out)	Provides read/write access to all LVDS channels. The least significant bit (LSB) of the U32 (HIHO)/U64 (All In and All Out) corresponds to DIO 0.
LVDS_Data_Rd	From CLIP	U32 (HIHO); U64 (All In)
Clk Out Inversion DO13 (HIHO)	To CLIP	Boolean	Inverts the generated clock by applying a 180-degree phase shift to the clock signal. The generated clocks are output on DO 13 (HIHO) or on DO 29 (All Out).
Clk Out Inversion DO29 (All Out)	To CLIP	Boolean
RX Data Clock	From CLIP	Clock	The acquisition clock for acquiring the LVDS input data. Refer to Figure 1 and Figure 5 for additional information.
TX Data Clock	From CLIP	Clock	The generation clock for generating the LVDS output data or acquiring the input data. This clock can be sourced from the Si514 or from the LMK04832 onboard clocking ICs. Refer to Figure 1, Figure 3, and Figure 5 for additional information.
TX/RX Delay Adjust Steps	To CLIP	U16	Sets the number of delay steps to apply to the corresponding TX/RX data line. This delay is applied after the corresponding TX/RX Delay Adjust Strobe is asserted. The delay can only be adjusted within the allowable delay limits of the FPGA. Adjusting outside these limits will not change the delay on the FPGA. Refer to the TX/RX Delay Value Rd signal description for additional information.
TX/RX Delay Increment	To CLIP	Boolean	TX/RX Delay Increment values: 1—Increments the line delay by the number of TX/RX Delay Adjust Steps when the TX/RX Delay Adjust Strobe is asserted. 0—Decrements the line delay by the number of TX/RX Delay Adjust Steps when the TX/RX Delay Adjust Strobe is asserted.
TX/RX Delay Adjust Strobe	To CLIP	Boolean	Applies the delay to the digital line. TX/RX Delay Adjust Steps and TX/RX Delay Increment should be configured before asserting the TX/RX Delay Adjust Strobe signal. After asserting this strobe signal, wait until TX/RX Delay Done has asserted before asserting TX/RX Delay Adjust Strobe again.
TX/RX Delay Value Rd	From CLIP	U16	Returns the delay count value in delay taps. The delay tap resolution can vary between 2.5 ps and 15 ps. Refer to the DS892 - Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics document at www.xilinx.com for additional information. The FPGA delay is restricted to the Align_Delay tap value as the lower limit and to 511 delay taps as the upper limit. Refer to the UG571 - Ultrascale Architecture SelectIO Resources user guide at www.xilinx.com for additional information on the Align_Delay tap value. The PXIe-6569 CLIP enforces the upper delay limit by preventing any further delay increments when the tap delay value of 511 is reached. The PXIe-6569 CLIP also enforces the lower delay limit by preventing any further delay decrements when the Align_Delay tap value is reached.
TX/RX Delay Done	From CLIP	Boolean	Reports when an increment/decrement operation has completed.

PXIe-6569 SERDES Socketed CLIP Signals


CLIP Signal Name	Direction	Data Type	Description
IO Ready	From CLIP	Boolean	Indicates successful configuration of the IO module with the current clocking mode settings.
IO Error	From CLIP	I32	Returns IO module errors, to be reported by the driver.
SE_Data_Output_Enable	To CLIP	Boolean	Provides read/write access to all single-ended channels. SE_Data_Output_Enable values: 1—Use SE_Data_Wr to write to the SE data line. 0—Use SE_Data_Rd to read the SE data line value.
SE_Data_Rd	From CLIP	Boolean
SE_Data_Wr	To CLIP	Boolean
LVDS_PFI_Output_Enable	To CLIP	Boolean	Provides read/write access to all low-voltage differential signal (LVDS) PFI channels. LVDS_PFI_Output_Enable values: 1—Use LVDS_PFI_Wr to write to the PFI data line. 0—Use LVDS_PFI_Rd to read the PFI data line value.
LVDS_PFI_Rd	From CLIP	Boolean
LVDS_PFI_Wr	To CLIP	Boolean
LVDS_Data_Wr	To CLIP	U8	Signals to read/write data from the LVDS channels. One U8 control/indicator represents the serialized/deserialized 8-bit data for an LVDS channel.
LVDS_Data_Rd	From CLIP	U8
Clk Out Inversion DO13 (HIHO)	To CLIP	Boolean	Inverts the generated clock by applying a 180-degree phase shift to the clock signal. The generated clocks are output on DO 13 (HIHO and All Out), DO 29 (All Out), and DO 54 (All Out).
Clk Out Inversion DO54 (All Out)	To CLIP	Boolean
Clk Out Inversion DO29 (All Out)	To CLIP	Boolean
Clk Out Inversion DO13 (All Out)	To CLIP	Boolean
RX Data Clock (HIHO)	From CLIP	Clock	The acquisition clock for acquiring the LVDS input data. This clock can be sourced from an external DI line or from the TX Data Clock. Refer to Figure 2 and Figure 5 for additional information.
RX Data Clock Bank 44 (All In)	From CLIP	Clock
RX Data Clock Bank 45 (All In)	From CLIP	Clock
RX Data Clock Bank 46 (All In)	From CLIP	Clock
TX Data Clock	From CLIP	Clock	The generation clock for generating the LVDS output data or acquiring the input data. This clock can be sourced from the Si514 or from the LMK04832 onboard clocking ICs. Refer to Figure 2, Figure 3, and Figure 5 for additional information.
TX/RX Delay Adjust Steps	To CLIP	U16	Sets the number of delay steps to apply to the corresponding TX/RX data line. This delay is applied after the corresponding TX/RX Delay Adjust Strobe is asserted. The delay can only be adjusted within the allowable delay limits of the FPGA. Adjusting outside these limits will not change the delay on the FPGA. Refer to the TX/RX Delay Value Rd signal description for additional information.
TX/RX Delay Increment	To CLIP	Boolean	TX/RX Delay Increment values: 1—Increments the line delay by the number of TX/RX Delay Adjust Steps when the TX/RX Delay Adjust Strobe is asserted. 0—Decrements the line delay by the number of TX/RX Delay Adjust Steps when the TX/RX Delay Adjust Strobe is asserted.
TX/RX Delay Adjust Strobe	To CLIP	Boolean	Applies the delay to the digital line. TX/RX Delay Adjust Steps and TX/RX Delay Increment should be configured before asserting the TX/RX Delay Adjust Strobe signal. After asserting this strobe signal, wait until TX/RX Delay Done has asserted before asserting TX/RX Delay Adjust Strobe again.
TX/RX Delay Value Rd	From CLIP	U16	Returns the delay count value in delay taps. The delay tap resolution can vary between 2.5 ps and 15 ps. Refer to the DS892 - Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics document at www.xilinx.com for additional information. The FPGA delay is restricted to the Align_Delay tap value as the lower limit and to 511 delay taps as the upper limit. Refer to the UG571 - Ultrascale Architecture SelectIO Resources user guide at www.xilinx.com for additional information on the Align_Delay tap value. The PXIe-6569 CLIP enforces the upper delay limit by preventing any further delay increments when the 511 tap delay value is reached. The PXIe-6569 CLIP also enforces the lower delay limit by preventing any further delay decrements when the Align_Delay tap value is reached.
TX/RX Delay Done	From CLIP	Boolean	Reports when an increment/decrement operation has completed.
Rx Bitslip	To CLIP	Boolean	Rotates the U8 captured data by one bit when asserted. This signal can be used to slip channels to align them in time.

Configuring Clocks

The PXIe-6569 TX/RX Data Clocks can be driven from multiple sources.

The following figures show the different clock sources available on both the Basic and the SERDES CLIPs for all modules.

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PXIe-6569 Getting Started Guide

PXIe, FlexRIO Digital Module (64 fixed-direction 1.25 Gbps LVDS, 8 PFI)

Table of Contents

Getting Started Guide

FlexRIO Documentation and Resources

Unpacking the Kit

What You Need to Get Started

Kit Contents

Recommended Cables

Installing the Software

Installing FlexRIO Modules

PXIe-6569 Front Panel and Connectors

Signal Descriptions

Verifying the Installation in MAX

Accessing FlexRIO with Integrated I/O Examples

PXIe-6569 Examples

Common FlexRIO with Integrated I/O Examples

FPGA Carrier Block Diagram

PXIe-6569 I/O Block Diagram

Component-Level Intellectual Property (CLIP)

PXIe-6569 CLIP

Socketed CLIP Signals

PXIe-6569 Basic Socketed CLIP Signals

PXIe-6569 SERDES Socketed CLIP Signals

Configuring Clocks

NI Services

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