Data Transfer Methods

Direct Memory Access

Direct Memory Access (DMA) is the default method of data transfer for PCI Express and PXI Express devices. DMA is a method to transfer data between the device and computer memory without the involvement of the CPU. This method makes DMA the fastest available data transfer method. NI uses DMA hardware and software technology to achieve high throughput rates and increase system utilization.

The PXIe-6368 has eight fully-independent DMA controllers for high-performance transfers of data blocks. One DMA controller is available for each measurement and acquisition block:

  • Analog input
  • Analog output
  • Counter 0
  • Counter 1
  • Counter 2
  • Counter 3
  • Digital waveform generation (digital output)
  • Digital waveform acquisition (digital input)

Each DMA controller channel contains a FIFO and independent processes for filling and emptying the FIFO. This allows the buses involved in the transfer to operate independently for maximum performance. Data is transferred simultaneously between the ports. The DMA controller supports burst transfers to and from the FIFO.

Each DMA controller supports several features to optimize PXI Express bus utilization. The DMA controllers pack and unpack data through the FIFOs. The DMA controllers also automatically handle unaligned memory buffers on PXI Express.

Programmed I/O

Programmed I/O is a data transfer mechanism where the user program is responsible for transferring data. Each read or write call in the program initiates the transfer of data. Programmed I/O is typically used in software-timed (on-demand) operations. Refer to the Analog Output Data Generation Methods section for more information.

PXIe DAQ Bandwidth Considerations

In order to continuously transfer large amounts of data, design the entire PXI Express system must be designed with sufficient data bandwidth.

Depending on the PXI Express connection to the PXI Express chassis backplane, bandwidth bottleneck may occur. This could be due to the DAQ task, the backplane connection, a PCIe switch integrated into the PXI Express backplane, or between the connection of a PXI Express remote controller to a host machine (if using MXI).

Different PXI Express chassis have different architectures and per slot bandwidths. Buffer overflow or underflow errors may occur as you approach or pass the maximum theoretical system bandwidth.

Note PXI Express specifications are developed by the PXI System Alliance. For more information, refer to the PXI Express Specification.