Each Programmable Function Interface (PFI) can be individually configured as the following:

  • A static digital input
  • A static digital output
  • A timing input signal for AI, DI, DO, or counter/timer functions
  • A timing output signal from AI, DI, DO, or counter/timer functions

Each PFI input also has a programmable debouncing filter. The following figure shows the circuitry of one PFI line. Each PFI line is similar.

Figure 76. PCIe-6350 PFI Circuitry


When a terminal is used as a timing input or output signal, it is called PFI x (where x is an integer from 0 to 15).

When a terminal is used as a static digital input or output, it is called P1.x or P2.x. On the I/O connector, each terminal is labeled PFI x/P1.x or PFI x/P2.x.

The voltage input and output levels and the current drive levels of the PFI signals are listed in the device specifications.

Note RTSI signals apply only to PCI or PCIe devices connected with RTSI cables. PXI_ and PXIe_ signals apply only to devices connected to a PXIe backplane.

Using PFI Terminals as Timing Input Signals

Use PFI terminals to route external timing signals to many different X Series functions. Each PFI terminal can be routed to any of the following signals:

  • AI Convert Clock (ai/ConvertClock)
  • AI Sample Clock (ai/SampleClock)
  • AI Sample Clock Timebase (ai/SampleClockTimebase)
  • AI Start Trigger (ai/StartTrigger)
  • AI Reference Trigger (ai/ReferenceTrigger)
  • AI Pause Trigger (ai/PauseTrigger)
  • Counter input signals for all counters—Source, Gate, Aux, HW_Arm, A, B, Z
  • Counter n Sample Clock
  • DI Sample Clock (di/SampleClock)
  • DI Sample Clock Timebase (di/SampleClockTimebase)
  • DI Reference Trigger (di/ReferenceTrigger)
  • DO Sample Clock (do/SampleClock)

Most functions allow you to configure the polarity of PFI inputs and whether the input is edge or level sensitive.

Exporting Timing Output Signals Using PFI Terminals

You can route any of the following timing signals to any PFI terminal configured as an output:

  • AI Convert Clock* (ai/ConvertClock)
  • AI Hold Complete Event (ai/HoldCompleteEvent)
  • AI Reference Trigger (ai/ReferenceTrigger)
  • AI Sample Clock (ai/SampleClock)
  • AI Start Trigger (ai/StartTrigger)
  • AI Pause Trigger (ai/PauseTrigger)
  • DI Sample Clock (di/SampleClock)
  • DI Start Trigger (di/StartTrigger)
  • DI Reference Trigger (di/ReferenceTrigger)
  • DI Pause Trigger (di/PauseTrigger)
  • DO Sample Clock* (do/SampleClock)
  • DO Start Trigger (do/StartTrigger)
  • DO Pause Trigger (do/PauseTrigger)
  • Counter n Source
  • Counter n Gate
  • Counter n Internal Output
  • Counter n Sample Clock
  • Counter n Counter n HW Arm
  • Frequency Output
  • PXI_STAR
  • RTSI <0..7>
  • Analog Comparison Event
  • Change Detection Event
  • Watchdog timer expired pulse
Note Signals with an * are inverted before being driven to a terminal; that is, these signals are active low.

Using PFI Terminals as Static Digital I/Os

Each PFI can be individually configured as a static digital input or a static digital output. When a terminal is used as a static digital input or output, it is called P1.x or P2.x. On the I/O connector, each terminal is labeled PFI x/P1.x or PFI x/P2.x.

In addition, PCIe-6350 devices have up to 32 lines of bidirectional DIO signals.

Using PFI Terminals to Digital Detection Events

Each PFI can be configured to detect digital changes. The values on the PFI lines cannot be read in a hardware-timed task, but they can be used to fire the change detection event. For example, if you wanted to do change detection on eight timed DIO lines but wanted to ensure that the value of the lines was updated every second independent of the eight lines changing you could set a PFI line up for change detection and connect a 1 Hz signal to it.

Connecting PFI Input Signals

All PFI input connections are referenced to D GND. The following figure shows this reference, and how to connect an external PFI 0 source and an external PFI 2 source to two PFI terminals.

Figure 77. PFI Input Signal Connections


I/O Protection

Each DIO and PFI signal is protected against overvoltage, undervoltage, and overcurrent conditions as well as ESD events. However, you should avoid these fault conditions by following these guidelines:

  • If you configure a PFI or DIO line as an output, do not connect it to any external signal source, ground, or power supply.
  • If you configure a PFI or DIO line as an output, understand the current requirements of the load connected to these signals. Do not exceed the specified current output limits of the DAQ device. NI has several signal conditioning solutions for digital applications requiring high current drive.
  • If you configure a PFI or DIO line as an input, do not drive the line with voltages outside of its normal operating range. The PFI or DIO lines have a smaller operating range than the AI signals.
  • Treat the DAQ device as you would treat any static sensitive device. Always properly ground yourself and the equipment when handling the DAQ device or connecting to it.

Programmable Power-Up States

At system startup and reset, the hardware sets all PFI and DIO lines to high-impedance inputs by default. The DAQ device does not drive the signal high or low. Each line has a weak pull-down resistor connected to it, as described in the device specifications.

NI-DAQmx supports programmable power-up states for PFI and DIO lines. Software can program any value at power up to the P0, P1, or P2 lines. The PFI and DIO lines can be set as:

  • A high-impedance input with a weak pull-down resistor (default)
  • An output driving a 0
  • An output driving a 1

Refer to the NI-DAQmx Help or the LabVIEW Help for more information about setting power-up states in NI-DAQmx or MAX.

Note When using an PCIe-6350 device to control an SCXI chassis, DIO lines 0, 1, 2, and 4 are used as communication lines and must be left to power-up in the default high-impedance state to avoid potential damage to these signals.