PCIe-5774 Specifications
- Updated2025-04-25
- 10 minute(s) read
Definitions
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.
Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
- Typical specifications describe the performance met by a majority of models.
- Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
- Measured specifications describe the measured performance of a representative model.
Specifications are Typical unless otherwise noted.
PCIe-5774 Pinout
Digital I/O
Connector | Molex™ Nano-Pitch I/O™ |
5.0 V Power | ±5%, 50 mA maximum, nominal |
Signal | Type | Direction |
---|---|---|
MGT Tx± <0..3>* | Xilinx UltraScale GTH | Output |
MGT Rx± <0..3>* | Xilinx UltraScale GTH | Input |
DIO <0..7> | Single-ended | Bidirectional |
5.0 V | DC | Output |
GND | Ground | — |
* Multi-gigabit transceiver (MGT) signals are available on devices with KU060 FPGAs only. |
Digital I/O Single-Ended Channels
Number of channels | 8 |
Signal type | Single-ended |
Voltage families | 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V |
Input impedance | 100 kΩ, nominal |
Output impedance | 50 Ω, nominal |
Direction control | Per channel |
Minimum required direction change latency | 200 ns |
Maximum output toggle rate | 60 MHz with 100 μA load, nominal |
Voltage Family (V) | VIL (V) | VIH (V) | VOL (100 µA Load) (V) | VOH (100 µA Load) (V) | Maximum DC Drive Strength (mA) |
---|---|---|---|---|---|
3.3 | 0.8 | 2.0 | 0.2 | 3.0 | 24 |
2.5 | 0.7 | 1.6 | 0.2 | 2.2 | 18 |
1.8 | 0.62 | 1.29 | 0.2 | 1.5 | 16 |
1.5 | 0.51 | 1.07 | 0.2 | 1.2 | 12 |
1.2 | 0.42 | 0.87 | 0.2 | 0.9 | 6 |
Digital I/O High-Speed Serial MGT
Data rate | 500 Mb/s to 16.375 Gb/s, nominal |
Number of Tx channels | 4 |
Number of Rx channels | 4 |
I/O AC coupling capacitor | 100 nF |
MGT TX± Channels
MGT RX± Channels
|
Differential input resistance | 100 Ω, nominal |
I/O coupling | DC-coupled, requires external capacitor |
Reconfigurable FPGA
PCIe-5774 modules are available with multiple FPGA options. The following table lists the FPGA specifications for the PCIe-5774 FPGA options.
KU035 | KU060 | |
---|---|---|
LUTs | 203,128 | 331,680 |
DSP48 slices (25 × 18 multiplier) | 1,700 | 2,760 |
Embedded Block RAM | 19.0 Mb | 38.0 Mb |
Data Clock Domain | 200 MHz, 16 samples per cycle per channel (dual channel mode), 32 samples per cycle (single channel mode) | |
Timebase reference sources | Onboard 100 MHz oscillator | |
Data transfers | DMA, interrupts, programmed I/O | DMA, interrupts, programmed I/O, multi-gigabit transceivers |
Number of DMA channels | 59 |
Onboard DRAM
Memory size | 4 GB (2 banks of 2 GB) |
DRAM clock rate | 1064 MHz |
Physical bus width | 32 bit |
LabVIEW FPGA DRAM clock rate | 267 MHz |
LabVIEW FPGA DRAM bus width | 256 bit per bank |
Maximum theoretical data rate | 17 GB/s (8.5 GB/s per bank) |
Analog Input
General Characteristics
Number of channels | 2, single-ended, simultaneously sampled | ||||||
Connector type | SMA | ||||||
Input impedance | 50 Ω, nominal | ||||||
Input coupling | DC | ||||||
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Analog-to-digital converter (ADC) | ADC12DJ3200, 12-bit resolution |
Typical Specifications
Full-scale input ranges | 200 mV peak-to-peak 1 V peak-to-peak | ||||||
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Vertical offset range | ±0.5 full-scale, nominal |
Input Frequency | ||||
---|---|---|---|---|
99.9 MHz | 399 MHz | 999 MHz | 1.999 GHz | |
SNR* (dBFS) | 54.7 | 54.4 | 53.9 | 52.8 |
SINAD* (dBFS) | 54.4 | 53.8 | 53.3 | 52.4 |
SFDR (dBc) | -65.2 | -61.1 | -60.3 | -63.2 |
ENOB† (bits) | 8.7 | 8.6 | 8.5 | 8.4 |
* Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. † Calculated from SINAD and corrected to full scale. |
Input Frequency | ||||
---|---|---|---|---|
99.9 MHz | 399 MHz | 999 MHz | 1.999 GHz | |
SNR* (dBFS) | 54.0 | 53.9 | 52.8 | 50.1 |
SINAD* (dBFS) | 53.9 | 53.4 | 52.2 | 50.0 |
SFDR (dBc) | -61.3 | -60.9 | -58.4 | -52.3 |
ENOB† (bits) | 8.7 | 8.6 | 8.4 | 8.0 |
Note: Measured using channel AI0. Spectral performance may be degraded using channel AI1. * Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. † Calculated from SINAD and corrected to full scale. |
Input Frequency | ||||
---|---|---|---|---|
99.9 MHz | 399 MHz | 999 MHz | 1.999 GHz | |
SNR* (dBFS) | 52.0 | 52.0 | 51.7 | 50.9 |
SINAD* (dBFS) | 51.9 | 51.8 | 51.4 | 50.7 |
SFDR (dBc) | -65.1 | -61.7 | -62 | -64.4 |
ENOB† (bits) | 8.3 | 8.3 | 8.2 | 8.1 |
* Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. † Calculated from SINAD and corrected to full scale. |
Input Frequency | ||||
---|---|---|---|---|
99.9 MHz | 399 MHz | 999 MHz | 1.999 GHz | |
SNR* (dBFS) | 51.0 | 51.0 | 50.4 | 48.9 |
SINAD* (dBFS) | 51.0 | 50.8 | 50.2 | 48.9 |
SFDR (dBc) | -57.8 | -58.8 | -58.4 | -53.3 |
ENOB† (bits) | 8.2 | 8.1 | 8.0 | 7.8 |
Note: Measured using channel AI0. Spectral performance may be degraded using channel AI1. * Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. † Calculated from SINAD and corrected to full scale. |
Mode |
|
|
|
---|---|---|---|
Dual channel | 15.3 | -143.3 | -147.3 |
Single channel | 10.2 | -146.8 | -150.8 |
Note: Excludes fixed interleaving spurs. |
Mode |
|
|
|
---|---|---|---|
Dual channel | 4.3 | -154.3 | -144.3 |
Single channel | 3.1 | -157.1 | -147.1 |
Note: Excludes fixed interleaving spurs. |




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REF/CLK IN
Connector type | SMA |
Input impedance | 50 Ω |
Input coupling | AC |
Input voltage range | 0.35 V peak-to-peak to 3.5 V peak-to-peak |
Absolute maximum voltage | ±12 V DC, 5 V peak-to-peak AC |
Duty cycle | 45% to 55% |
Onboard reference timebase stability | ±0.7 ppm |
Sample Clock jitter[5]5 Integrated from 3.2 kHz to 20 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter. Excludes trigger jitter. | 85 fs RMS, measured |
Clock Configuration | External Clock Frequency | Description |
---|---|---|
Internal Reference Clock* | — | The internal Sample Clock locks to an onboard voltage-controlled temperature compensated crystal oscillator (VCTCXO). |
Internal Baseboard Reference Clock | 10 MHz | The internal Sample Clock locks to the 10 MHz Reference Clock, which is provided through the FPGA baseboard. |
External Reference Clock (REF/CLK IN) | 10 MHz† | The internal Sample Clock locks to an external Reference Clock, which is provided through the REF/CLK IN front panel connector. |
External Sample Clock (REF/CLK IN) | 3.2 GHz | An external Sample Clock can be provided through the REF/CLK IN front panel connector. |
* Default clock configuration. † The external Reference Clock must be accurate to ±25 ppm. |

Analog IN Trigger
Connector type | SMA |
Input impedance | 50 Ω, nominal |
Input coupling | DC |
Input voltage range | ±5 V |
Comparator threshold resolution | 12 bits |
Minimum pulse width | 5 ns |
Absolute maximum voltage | ±6 V |
Digital OUT Trigger
Connector type | SMA |
Input impedance | 50 Ω, nominal |
Input coupling | DC |
Logic type | 3.3 V CMOS |
Maximum current drive | 24 mA |
Update rate resolution | 5 ns |
Jitter | 3.2 ps RMS, measured |
Bus Interface
Card edge form factor | PCI Express Gen-3 x8 |
Slot compatibility | x8, and x16 PCI Express slots |
Maximum Power Requirements
+3.3 V | 4.5 A |
+12 V | 5 A |
Maximum total power | 75 W |
Physical
Dimensions (including I/O bracket, not including connectors) | 12.6 cm × 26.3 cm × 4 cm (5.0 in. × 10.4 in. × 1.6 in.) |
Weight | 990 g (35 oz) |
PCI Express mechanical form factor | Standard height, three-quarter length, double slot |
Integrated air mover (fan) | Yes |
Maximum rear panel exhaust airflow | 84 m3/h (50 CFM) (without any chassis impedance) |
Environment
Maximum altitude | 2,000 m (800 mbar) (at 25 °C ambient temperature) |
Pollution Degree | 2 |
Indoor use only.
Operating Environment
Operating temperature, local[6]6 For PCI Express adapter cards with integrated air movers, NI defines the local operational ambient environment to be at the fan inlet. For cards without integrated air movers, NI defines the local operational ambient environment to be 25 mm (1 in.) upstream of the leading edge of the card. | 0 °C to 45 °C |
Operating humidity | 10% to 90% RH, noncondensing |
Storage Environment
Ambient temperature range | -20 °C to 70 °C |
Relative humidity range | 5% to 95% RH, noncondensing |
1 Voltage levels are guaranteed by design through the digital buffer specifications.
2 800 mV peak-to-peak when transmitter output swing is set to the maximum setting.
3 In single channel mode the ADC cores are interleaved for an aggregate sample rate of 6.4 GS/s.
4 Normalized to 10 MHz.
5 Integrated from 3.2 kHz to 20 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter. Excludes trigger jitter.
6 For PCI Express adapter cards with integrated air movers, NI defines the local operational ambient environment to be at the fan inlet. For cards without integrated air movers, NI defines the local operational ambient environment to be 25 mm (1 in.) upstream of the leading edge of the card.