PCIe-5774 Specifications

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Updated2025-04-25
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Definitions

Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

Typical specifications describe the performance met by a majority of models.
Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
Measured specifications describe the measured performance of a representative model.

Specifications are Typical unless otherwise noted.

PCIe-5774 Pinout

Figure 1. PCIe-5774 Digital I/O Connector Pinout

Notice The maximum input signal levels are valid only when the module is powered on. To avoid permanent damage to the PCIe-5774, do not apply a signal to the device when the module is powered down.

Notice Connections that exceed any of the maximum ratings of any connector on the PCIe-5774 can damage the device and the system. NI is not liable for any damage resulting from such connections.

Note MGTs are available only on devices with KU040 and KU060 FPGAs.

Digital I/O

Connector	Molex™ Nano-Pitch I/O™
5.0 V Power	±5%, 50 mA maximum, nominal

Table 1. Digital I/O Signal Characteristics
Signal	Type	Direction
MGT Tx± <0..3>^*	Xilinx UltraScale GTH	Output
MGT Rx± <0..3>^*	Xilinx UltraScale GTH	Input
DIO <0..7>	Single-ended	Bidirectional
5.0 V	DC	Output
GND	Ground	—
^* Multi-gigabit transceiver (MGT) signals are available on devices with KU060 FPGAs only.

Digital I/O Single-Ended Channels

Number of channels	8
Signal type	Single-ended
Voltage families	3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V
Input impedance	100 kΩ, nominal
Output impedance	50 Ω, nominal
Direction control	Per channel
Minimum required direction change latency	200 ns
Maximum output toggle rate	60 MHz with 100 μA load, nominal

Table 2. Digital I/O Single-Ended DC Signal Characteristics^[1]¹ Voltage levels are guaranteed by design through the digital buffer specifications.
Voltage Family (V)	V_IL (V)	V_IH (V)	V_OL (100 µA Load) (V)	V_OH (100 µA Load) (V)	Maximum DC Drive Strength (mA)
3.3	0.8	2.0	0.2	3.0	24
2.5	0.7	1.6	0.2	2.2	18
1.8	0.62	1.29	0.2	1.5	16
1.5	0.51	1.07	0.2	1.2	12
1.2	0.42	0.87	0.2	0.9	6

Digital I/O High-Speed Serial MGT

Note For detailed FPGA and High-Speed Serial Link specifications, refer to Xilinx documentation.

Note MGTs are available on devices with KU060 FPGAs only.

Data rate	500 Mb/s to 16.375 Gb/s, nominal
Number of Tx channels	4
Number of Rx channels	4
I/O AC coupling capacitor	100 nF

MGT TX± Channels

Minimum differential output voltage^[2]² 800 mV peak-to-peak when transmitter output swing is set to the maximum setting.	170 mV peak-to-peak into 100 Ω, nominal
I/O coupling	AC-coupled, includes 100 nF capacitor

MGT RX± Channels

Differential input voltage range
≤ 6.6 Gb/s	150 mV peak-to-peak to 2000 mV peak-to-peak, nominal
> 6.6 Gb/s	150 mV peak-to-peak to 1250 mV peak-to-peak, nominal


Differential input resistance	100 Ω, nominal
I/O coupling	DC-coupled, requires external capacitor

Reconfigurable FPGA

PCIe-5774 modules are available with multiple FPGA options. The following table lists the FPGA specifications for the PCIe-5774 FPGA options.

Table 3. Reconfigurable FPGA Options
	KU035	KU060
LUTs	203,128	331,680
DSP48 slices (25 × 18 multiplier)	1,700	2,760
Embedded Block RAM	19.0 Mb	38.0 Mb
Data Clock Domain	200 MHz, 16 samples per cycle per channel (dual channel mode), 32 samples per cycle (single channel mode)
Timebase reference sources	Onboard 100 MHz oscillator
Data transfers	DMA, interrupts, programmed I/O	DMA, interrupts, programmed I/O, multi-gigabit transceivers
Number of DMA channels	59

Note The Reconfigurable FPGA Options table depicts the total number of FPGA resources available on the part. The number of resources available to the user is slightly lower, as some FPGA resources are consumed by board-interfacing IP for PCI Express, device configuration, and various board I/O. For more information, contact NI support.

Onboard DRAM

Memory size	4 GB (2 banks of 2 GB)
DRAM clock rate	1064 MHz
Physical bus width	32 bit
LabVIEW FPGA DRAM clock rate	267 MHz
LabVIEW FPGA DRAM bus width	256 bit per bank
Maximum theoretical data rate	17 GB/s (8.5 GB/s per bank)

Analog Input

General Characteristics

Number of channels

2, single-ended, simultaneously sampled

Connector type

SMA

Input impedance

50 Ω, nominal

Input coupling

Sample Clock
Internal Sample Clock³ In single channel mode the ADC cores are interleaved for an aggregate sample rate of 6.4 GS/s.^[3]	3.2 GHz
External Sample Clock^[3]	3.2 GHz

Sample Rate
Dual channel mode	3.2 GS/s per channel
Single channel mode	6.4 GS/s


Analog-to-digital converter (ADC)	ADC12DJ3200, 12-bit resolution

Typical Specifications

Full-scale input ranges

200 mV peak-to-peak

1 V peak-to-peak

Gain accuracy
200 mV range	±1.47%
1 V range	±1.44%

DC offset
200 mV range	±0.628 mV
1 V range	±1.269 mV


Vertical offset range	±0.5 full-scale, nominal

Bandwidth (-3 dB)^[4]⁴ Normalized to 10 MHz.

-01 variant

200 mV range: 3.00 GHz

1 V range: 2.85 GHz

-02 variant

200 mV range: 1.63 GHz

1 V range: 1.62 GHz

Table 4. Single-Tone Spectral Performance, Dual Channel Mode, 1 V range, -01 Variant
	Input Frequency
	99.9 MHz	399 MHz	999 MHz	1.999 GHz
SNR^* (dBFS)	54.7	54.4	53.9	52.8
SINAD^* (dBFS)	54.4	53.8	53.3	52.4
SFDR (dBc)	-65.2	-61.1	-60.3	-63.2
ENOB^† (bits)	8.7	8.6	8.5	8.4
^* Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. ^† Calculated from SINAD and corrected to full scale.

Table 5. Single-Tone Spectral Performance, Single Channel Mode, 1 V range, -01 Variant
	Input Frequency
	99.9 MHz	399 MHz	999 MHz	1.999 GHz
SNR^* (dBFS)	54.0	53.9	52.8	50.1
SINAD^* (dBFS)	53.9	53.4	52.2	50.0
SFDR (dBc)	-61.3	-60.9	-58.4	-52.3
ENOB^† (bits)	8.7	8.6	8.4	8.0
Note: Measured using channel AI0. Spectral performance may be degraded using channel AI1. ^* Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. ^† Calculated from SINAD and corrected to full scale.

Table 6. Single-Tone Spectral Performance, Dual Channel Mode, 200 mV range, -01 Variant
	Input Frequency
	99.9 MHz	399 MHz	999 MHz	1.999 GHz
SNR^* (dBFS)	52.0	52.0	51.7	50.9
SINAD^* (dBFS)	51.9	51.8	51.4	50.7
SFDR (dBc)	-65.1	-61.7	-62	-64.4
ENOB^† (bits)	8.3	8.3	8.2	8.1
^* Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. ^† Calculated from SINAD and corrected to full scale.

Table 7. Single-Tone Spectral Performance, Single Channel Mode, 200 mV range, -01 Variant
	Input Frequency
	99.9 MHz	399 MHz	999 MHz	1.999 GHz
SNR^* (dBFS)	51.0	51.0	50.4	48.9
SINAD^* (dBFS)	51.0	50.8	50.2	48.9
SFDR (dBc)	-57.8	-58.8	-58.4	-53.3
ENOB^† (bits)	8.2	8.1	8.0	7.8
Note: Measured using channel AI0. Spectral performance may be degraded using channel AI1. ^* Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth. ^† Calculated from SINAD and corrected to full scale.

Table 8. Noise Spectral Density, 1 V Range, -01 Variant
Mode	$\frac{n V}{\sqrt{H z}}$	$\frac{d B m}{H z}$	$\frac{d B F S}{H z}$
Dual channel	15.3	-143.3	-147.3
Single channel	10.2	-146.8	-150.8
Note: Excludes fixed interleaving spurs.

Table 9. Noise Spectral Density, 200 mV Range, -01 Variant
Mode	$\frac{n V}{\sqrt{H z}}$	$\frac{d B m}{H z}$	$\frac{d B F S}{H z}$
Dual channel	4.3	-154.3	-144.3
Single channel	3.1	-157.1	-147.1
Note: Excludes fixed interleaving spurs.

Note Noise spectral density is verified using a 50 Ω terminator connected to AI0. Noise Spectral density may be degraded using channel AI1.

Figure 2. Single Tone Spectrum (Dual Channel Mode, 99MHz, -1 dBFS, 1 V Range, 3.2 kHz RBW, -01 Variant), Measured

Figure 3. Single Tone Spectrum (Dual Channel Mode, 999 MHz, -1 dBFS, 1 V Range, 3.2 kHz RBW, -01 Variant), Measured

Figure 4. Single Tone Spectrum (Single Channel Mode, 99 MHz, -1 dBFS, 1 V Range, 3.2 kHz RBW, -01 Variant), Measured

Figure 5. Single Tone Spectrum (Single Channel Mode, 999 MHz, -1 dBFS, 1 V Range, 3.2 kHz RBW, -01 Variant), Measured

Channel-to-channel crosstalk, measured
99.9 MHz	-94.1 dB
399 MHz	-85.6 dB
999 MHz	-82.5 dB
1.59 GHz	-75.6 dB
1.99 GHz	-72.2 dB

Figure 6. Analog Input Frequency Response (1 V Range, -01 Variant), Measured

Figure 7. Analog Input Frequency Response (200 mV Range, -01 Variant), Measured

Figure 8. Analog Input Frequency Response (1 V Range, -02 Variant), Measured

Figure 9. Analog Input Frequency Response (200 mV Range, -02 Variant), Measured

Figure 10. Input Return Loss (1 V Range), Measured

Figure 11. Input Return Loss (200 mV Range), Measured

REF/CLK IN

Connector type	SMA
Input impedance	50 Ω
Input coupling	AC
Input voltage range	0.35 V peak-to-peak to 3.5 V peak-to-peak
Absolute maximum voltage	±12 V DC, 5 V peak-to-peak AC
Duty cycle	45% to 55%
Onboard reference timebase stability	±0.7 ppm
Sample Clock jitter^[5]⁵ Integrated from 3.2 kHz to 20 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter. Excludes trigger jitter.	85 fs RMS, measured

Table 10. Clock Configuration Options
Clock Configuration	External Clock Frequency	Description
Internal Reference Clock^*	—	The internal Sample Clock locks to an onboard voltage-controlled temperature compensated crystal oscillator (VCTCXO).
Internal Baseboard Reference Clock	10 MHz	The internal Sample Clock locks to the 10 MHz Reference Clock, which is provided through the FPGA baseboard.
External Reference Clock (REF/CLK IN)	10 MHz^†	The internal Sample Clock locks to an external Reference Clock, which is provided through the REF/CLK IN front panel connector.
External Sample Clock (REF/CLK IN)	3.2 GHz	An external Sample Clock can be provided through the REF/CLK IN front panel connector.
^* Default clock configuration. ^† The external Reference Clock must be accurate to ±25 ppm.

Figure 12. Phase Noise with 800 MHz Input Tone, Measured

Analog IN Trigger

Connector type	SMA
Input impedance	50 Ω, nominal
Input coupling	DC
Input voltage range	±5 V
Comparator threshold resolution	12 bits
Minimum pulse width	5 ns
Absolute maximum voltage	±6 V

Digital OUT Trigger

Connector type	SMA
Input impedance	50 Ω, nominal
Input coupling	DC
Logic type	3.3 V CMOS
Maximum current drive	24 mA
Update rate resolution	5 ns
Jitter	3.2 ps RMS, measured

Bus Interface

Card edge form factor	PCI Express Gen-3 x8
Slot compatibility	x8, and x16 PCI Express slots

Maximum Power Requirements

Note Power requirements depend on the contents of the LabVIEW FPGA VI used in your application.

+3.3 V	4.5 A
+12 V	5 A
Maximum total power	75 W

Physical

Dimensions (including I/O bracket, not including connectors)	12.6 cm × 26.3 cm × 4 cm (5.0 in. × 10.4 in. × 1.6 in.)
Weight	990 g (35 oz)
PCI Express mechanical form factor	Standard height, three-quarter length, double slot
Integrated air mover (fan)	Yes
Maximum rear panel exhaust airflow	84 m³/h (50 CFM) (without any chassis impedance)

Environment

Maximum altitude	2,000 m (800 mbar) (at 25 °C ambient temperature)
Pollution Degree	2

Indoor use only.

Operating Environment

Operating temperature, local^[6]⁶ For PCI Express adapter cards with integrated air movers, NI defines the local operational ambient environment to be at the fan inlet. For cards without integrated air movers, NI defines the local operational ambient environment to be 25 mm (1 in.) upstream of the leading edge of the card.	0 °C to 45 °C
Operating humidity	10% to 90% RH, noncondensing

Storage Environment

Ambient temperature range	-20 °C to 70 °C
Relative humidity range	5% to 95% RH, noncondensing

¹ Voltage levels are guaranteed by design through the digital buffer specifications.

² 800 mV peak-to-peak when transmitter output swing is set to the maximum setting.

³ In single channel mode the ADC cores are interleaved for an aggregate sample rate of 6.4 GS/s.

⁴ Normalized to 10 MHz.

⁵ Integrated from 3.2 kHz to 20 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter. Excludes trigger jitter.

⁶ For PCI Express adapter cards with integrated air movers, NI defines the local operational ambient environment to be at the fan inlet. For cards without integrated air movers, NI defines the local operational ambient environment to be 25 mm (1 in.) upstream of the leading edge of the card.