PCIe-5764 Specifications

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Updated2025-04-24
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Definitions

Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

Typical specifications describe the performance met by a majority of models.
Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
Measured specifications describe the measured performance of a representative model.

Specifications are Typical unless otherwise noted.

PCIe-5764 Pinout

Figure 1. PCIe-5764 Digital I/O Connector Pinout

Notice The maximum input signal levels are valid only when the module is powered on. To avoid permanent damage to the PCIe-5764, do not apply a signal to the device when the module is powered down.

Notice Connections that exceed any of the maximum ratings of any connector on the PCIe-5764 can damage the device and the system. NI is not liable for any damage resulting from such connections.

Note MGTs are available only on devices with KU040 and KU060 FPGAs.

Digital I/O

Connector	Molex™ Nano-Pitch I/O™
5.0 V Power	±5%, 50 mA maximum, nominal

Table 1. Digital I/O Signal Characteristics
Signal	Type	Direction
MGT Tx± <3..0>^*	Xilinx UltraScale GTH	Output
MGT Rx± <3..0>^*	Xilinx UltraScale GTH	Input
DIO <7..0>	Single-ended	Bidirectional
5.0 V	DC	Output
GND	Ground	—
^* Multi-gigabit transceiver (MGT) signals are available on devices with KU040 and KU060 FPGAs only.

Digital I/O Single-Ended Channels

Number of channels	8
Signal type	Single-ended
Voltage families	3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V
Input impedance	100 kΩ, nominal
Output impedance	50 Ω, nominal
Direction control	Per channel
Minimum required direction change latency	200 ns
Maximum output toggle rate	60 MHz with 100 μA load, nominal

Table 2. Digital I/O Single-Ended DC Signal Characteristics^[1]¹ Voltage levels are guaranteed by design through the digital buffer specifications.
Voltage Family (V)	V_IL (V)	V_IH (V)	V_OL (100 µA Load) (V)	V_OH (100 µA Load) (V)	Maximum DC Drive Strength (mA)
3.3	0.8	2.0	0.2	3.0	24
2.5	0.7	1.6	0.2	2.2	18
1.8	0.62	1.29	0.2	1.5	16
1.5	0.51	1.07	0.2	1.2	12
1.2	0.42	0.87	0.2	0.9	6

Digital I/O High-Speed Serial MGT

Note For detailed FPGA and High-Speed Serial Link specifications, refer to Xilinx documentation.

Note MGTs are available on devices with KU040 and KU060 FPGAs only.

Data rate	500 Mb/s to 16.375 Gb/s, nominal
Number of Tx channels	4
Number of Rx channels	4
I/O AC coupling capacitor	100 nF

MGT TX± Channels

Minimum differential output voltage^[2]² 800 mV peak-to-peak when transmitter output swing is set to the maximum setting.	170 mV peak-to-peak into 100 Ω, nominal
I/O coupling	AC-coupled, includes 100 nF capacitor

MGT RX± Channels

Differential input voltage range
≤ 6.6 Gb/s	150 mV peak-to-peak to 2000 mV peak-to-peak, nominal
> 6.6 Gb/s	150 mV peak-to-peak to 1250 mV peak-to-peak, nominal


Differential input resistance	100 Ω, nominal
I/O coupling	DC-coupled, requires external capacitor

Reconfigurable FPGA

PCIe-5764 modules are available with multiple FPGA options. The following table lists the FPGA specifications for the PCIe-5764 FPGA options.

Table 3. Reconfigurable FPGA Options
	KU035	KU040	KU060
LUTs	203,128	242,200	331,680
DSP48 slices (25 × 18 multiplier)	1,700	1,920	2,760
Embedded Block RAM	19.0 Mb	21.1 Mb	38.0 Mb
Default timebase	80 MHz
Timebase reference sources	Onboard 100 MHz oscillator
Data transfers	DMA, interrupts, programmed I/O	DMA, interrupts, programmed I/O, multi-gigabit transceivers
Number of DMA channels	59

Note The Reconfigurable FPGA Options table depicts the total number of FPGA resources available on the part. The number of resources available to the user is slightly lower, as some FPGA resources are consumed by board-interfacing IP for PCI Express, device configuration, and various board I/O. For more information, contact NI support.

Note For FPGA designs using the majority of KU040 or KU060 FPGA resources while running at clock rates over 150 MHz, the module may require more power than is available. If the module attempts to draw more than allowed per its specification, the module protects itself and reverts to a default FPGA personality. Refer to the getting started guide for your module or contact NI support for more information.

Onboard DRAM

Memory size	4 GB (2 banks of 2 GB)
DRAM clock rate	1064 MHz
Physical bus width	32 bit
LabVIEW FPGA DRAM clock rate	267 MHz
LabVIEW FPGA DRAM bus width	256 bit per bank
Maximum theoretical data rate	17 GB/s (8.5 GB/s per bank)

Analog Input

Notice The maximum input signal levels are valid only when the module is powered on. To avoid permanent damage to the PCIe-5764, do not apply a signal to the device when the module is powered down.

General Characteristics

Number of channels

4, single-ended, simultaneously sampled

Connector type

SMA

Input impedance

50 Ω

Input coupling

AC or DC^[3]³ Only one analog input path type is populated.

Sample rate
Internal Sample Clock	1 GHz
External Sample Clock	1 GHz


Analog-to-digital converter (ADC)	ADS54J60, 16-bit resolution

Typical Specifications

Full-scale input range (normal operating conditions)
AC-coupled	2.05 V_pp (10.22 dBm) at 10 MHz
DC-coupled	2.00 V_pp (10 dBm)

Gain accuracy
AC-coupled	±0.1 dB at 10 MHz
DC-coupled	±0.79% at DC

DC offset
AC-coupled	±22 µV
DC-coupled	±363 µV

Bandwidth (-3 dB)^[4]⁴ Normalized to 10 MHz.
AC-coupled	0.07 MHz to 1.15 GHz^[5]⁵ Maximum bandwidth for full scale input signal is 400 MHz. See the ADS54J60 datasheet for details on maximum supported amplitude for frequencies greater than 400 MHz.
DC-coupled	DC to 400 MHz

Table 4. Single Tone Spectral Performance
	AC-Coupled			DC-Coupled
	Input Frequency			Input Frequency
	10.1 MHz	123.1 MHz	199.1 MHz	10.1 MHz	123.1 MHz	199.1 MHz
SNR^* (dBFS)	69.8	68.7	67	68.7	67.5	65.8
SINAD^* (dBFS)	68.7	67.6	66.7	68.1	67.1	65.3
SFDR (dBc)	-80.7	-81.8	-75.6	-76.6	-75.8	-73.4
ENOB^† (Bits)	11.1	10.9	10.8	11.0	10.9	10.6
^* Measured with a -1 dBFS signal and corrected to full-scale. 1 kHz resolution bandwidth. ^† Calculated from SINAD and corrected to full-scale.

Note Excludes ADC interleaving spurs.

Table 5. Noise Spectral Density
Module	nV/rt (Hz)	dBm/Hz	dBFS/Hz
AC-coupled	9.7	-147.3	-157.5
DC-coupled	11.9	-145.5	-155.5

Note Noise spectral density is verified using a 50 Ω terminator connected to the input.

Figure 2. AC-Coupled Single Tone Spectrum (10.1 MHz, -1 dBFS, 1 kHz RBW), Measured

Figure 3. AC-Coupled Single Tone Spectrum (123.1 MHz, -1 dBFS, 1 kHz RBW), Measured

Figure 4. AC-Coupled Single Tone Spectrum (199.1 MHz, -1 dBFS, 1 kHz RBW), Measured

Figure 5. DC-Coupled Single Tone Spectrum (10.1 MHz, -1 dBFS, 1 kHz RBW), Measured

Figure 6. DC-Coupled Single Tone Spectrum (123.1 MHz, -1 dBFS, 1 kHz RBW), Measured

Figure 7. DC-Coupled Single Tone Spectrum (199.1 MHz, -1 dBFS, 1 kHz RBW), Measured

Channel-to-channel crosstalk AC-coupled, measured
1 MHz	-87 dB
100 MHz	-90 dB
250 MHz	-85 dB
400 MHz	-84 dB

Channel-to-channel crosstalk DC-coupled, measured
1 MHz	-88 dB
100 MHz	-84 dB
250 MHz	-75 dB
400 MHz	-75 dB

Figure 8. AC-Coupled Frequency Response, Measured

Figure 9. AC-Coupled Passband Flatness for Full Scale Input Supported Frequency Range, Measured

Figure 10. DC-Coupled Frequency Response, Measured

Figure 11. DC-Coupled Frequency Response Zoomed In, Measured

REF/CLK IN

General Characteristics

Connector type

SMA

Input impedance

50 Ω

Input coupling

Reference input voltage range

0.3 V_pp to 4 V_pp

Sample Clock input voltage range

0.3 V_pp to 4 V_pp

Absolute maximum voltage

±12 V DC, 4 V_pp AC

Duty cycle

45% to 55%

Onboard reference timebase stability

±0.7 ppm

Sample Clock jitter^[6]⁶ Integrated from 1 kHz to 10 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter. Excludes trigger jitter.
AC-coupled	140 fs RMS
DC-coupled	143 fs RMS

Table 6. Clock Configuration Options
Clock Configuration	External Clock Type	External Clock Frequency	Description
Internal Reference Clock^*	—	—	The internal Sample Clock locks to an onboard voltage-controlled temperature compensated crystal oscillator (VCTCXO).
Internal Baseboard Reference Clock	—	10 MHz	The internal Sample Clock locks to the 10 MHz Reference Clock provided from the FPGA baseboard.
External Reference Clock (REF/CLK IN)	Reference Clock	10 MHz^†	The internal Sample Clock locks to an external Reference Clock, which is provided through the REF/CLK IN front panel connector.
External Sample Clock (REF/CLK IN)	Sample Clock	1 GHz	An external Sample Clock can be provided through the REF/CLK IN front panel connector.
^* Default clock configuration. ^† The PLL Reference Clock must be accurate to ±25 ppm.

Figure 13. AC-Coupled Phase Noise with 385.6 MHz Input Tone, Measured

Figure 14. DC-Coupled Phase Noise with 385.6 MHz Input Tone, Measured

Bus Interface

Card edge form factor	PCI Express Gen-3 x8
Slot compatibility	x8 and x16 PCI Express

Maximum Power Requirements

Note Power requirements depend on the contents of the LabVIEW FPGA VI used in your application.

+3.3 V	4.5 A
+12 V	5 A
Maximum total power	75 W

Physical

Dimensions (including I/O bracket, not including connectors)	12.6 cm × 26.3 cm × 4 cm (5.0 in. × 10.4 in. × 1.6 in.)
Weight	990 g (35 oz)
PCI Express mechanical form factor	Standard height, three-quarter length, double slot
Integrated air mover (fan)	Yes
Maximum rear panel exhaust airflow	84 m³/h (50 CFM) (without any chassis impedance)

Environment

Maximum altitude	2,000 m (800 mbar) (at 25 °C ambient temperature)
Pollution Degree	2

Indoor use only.

Operating Environment

Operating temperature, local^[7]⁷ For PCI Express adapter cards with integrated air movers, NI defines the local operational ambient environment to be at the fan inlet. For cards without integrated air movers, NI defines the local operational ambient environment to be 25 mm (1 in.) upstream of the leading edge of the card.	0 °C to 45 °C
Operating humidity	10% to 90% RH, noncondensing

Storage Environment

Ambient temperature range	-20 °C to 70 °C
Relative humidity range	5% to 95% RH, noncondensing

¹ Voltage levels are guaranteed by design through the digital buffer specifications.

² 800 mV peak-to-peak when transmitter output swing is set to the maximum setting.

³ Only one analog input path type is populated.

⁴ Normalized to 10 MHz.

⁵ Maximum bandwidth for full scale input signal is 400 MHz. See the ADS54J60 datasheet for details on maximum supported amplitude for frequencies greater than 400 MHz.

⁶ Integrated from 1 kHz to 10 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter. Excludes trigger jitter.

⁷ For PCI Express adapter cards with integrated air movers, NI defines the local operational ambient environment to be at the fan inlet. For cards without integrated air movers, NI defines the local operational ambient environment to be 25 mm (1 in.) upstream of the leading edge of the card.