PCI/PXI/USB-6281 Specifications

PCI/PXI/USB-6281 Specifications

These specifications apply to the PCI/PXI/USB-6281.

The following specifications are typical at 25 °C, unless otherwise noted.

Revision History

Version Date changed Description
375218F-01 October 2025 Updated I/O connector specifications.
375218E-01 June 2025 Added pinout.
375218D-01 September 2024 Updated Compliance content.
375218C-01 June 2016 Updated Compliance content.
375218B-01 September 2015 Updated legal notifications.
375218A-01 May 2015 Initial release (PCI/PXI/USB-6281 only).
371292G-01 June 2007 Original specifications document: NI 628x Specifications.

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PCI/PXI/USB-6281 Pinout

Figure 1. PCI/PXI-6281 Pinout


Figure 2. USB-6281 Mass Termination Pinout


Figure 3. USB-6281 Screw Terminal Pinout


Analog Input

Table 1. Analog Input
Number of channels 8 differential or 16 single ended
ADC resolution 18 bits
DNL No missing codes guaranteed
INL Refer to AI Absolute Accuracy
Input coupling DC
Input range ±0.1 V, ±0.2 V, ±0.5 V, ±1 V, ±2 V, ±5 V, ±10 V
Maximum working voltage for analog inputs (signal + common mode) ±11 V of AI GND
CMRR (DC to 60 Hz) 110 dB
Input bias current ±100 pA
Small signal bandwidth (-3 dB) 750 kHz filter off, 40 kHz filter on
Input FIFO size 2,047 samples
Scan list memory 4,095 entries
Table 2. AI Sample Rate
Single channel maximum 625 kS/s
Multichannel maximum (aggregate) 500 kS/s
Minimum No minimum
Table 3. AI Timing
Timing accuracy 50 ppm of sample rate
Timing resolution 50 ns
Table 4. AI Input Impedance
Device on, AI+ to AI GND >10 GΩ in parallel with 100 pF
Device on, AI- to AI GND >10 GΩ in parallel with 100 pF
Device off, AI+ to AI GND 820 Ω
Device off, AI- to AI GND 820 Ω
Table 5. AI Crosstalk (at 100 kHz)
Adjacent channels -75 dB
Non-adjacent channels -95 dB
Table 6. AI Data Transfers
PCI/PXI DMA (scatter-gather), interrupts, programmed I/O
USB USB Signal Stream, programmed I/O
Table 7. AI Overvoltage Protection for All Analog Input and Sense Channels
Device on ±25 V for up to eight AI pins
Device off ±15 V for up to eight AI pins
Table 8. AI Input Current During Overvoltage Condition
Input current during overvoltage condition ±20 mA maximum/AI pin

Settling Time for Multichannel Measurements

Table 9. Settling Time for Multichannel Measurements
Range Filter Off ±15 ppm of Step (±4 LSB for Full-Scale Step) Filter Off ±4 ppm of Step (±1 LSB for Full-Scale Step) Filter On ±4 ppm of Step (±1 LSB for Full-Scale Step)
±5 V, ±10 V 2 μs 8 μs 50 μs
±0.5 V, ±1 V, ±2 V 2.5 μs 8 μs 50 μs
±0.1 V, ±0.2 V 3 μs 8 μs 50 μs

Typical Performance Graphs

Figure 4. AI Settling Error versus Time for Different Source Impedances


Figure 5. AI Small Signal Bandwidth


Figure 6. AI CMRR


AI Absolute Accuracy

AI Absolute Accuracy (Filter On)

Note Accuracies listed are valid for up to two years from the device external calibration.
Table 10. AI Absolute Accuracy (Filter On)
Nominal Range Positive Full Scale Nominal Range Negative Full Scale Residual Gain Error (ppm of Reading) Residual Offset Error (ppm of Range) Offset Tempco (ppm of Range/°C) Random Noise, σ (μVrms) Absolute Accuracy at Full Scale (μV) Sensitivity (μV)
10 -10 40 8 11 60 980 24
5 -5 45 8 11 30 510 12
2 -2 45 8 13 12 210 4.8
1 -1 55 15 15 7 120 2.8
0.5 -0.5 55 30 20 4 70 1.6
0.2 -0.2 75 45 35 3 39 1.2
0.1 -0.1 120 60 60 2 28 0.8
Note Sensitivity is the smallest voltage change that can be detected. It is a function of noise.
Table 11. AI Absolute Accuracy Values (Filter On)
Gain tempco 17 ppm/°C
Reference tempco 1 ppm/°C
INL error 10 ppm of range

AI Absolute Accuracy (Filter Off)

Note Accuracies listed are valid for up to two years from the device external calibration.
Table 12. AI Absolute Accuracy (Filter Off)
Nominal Range Positive Full Scale Nominal Range Negative Full Scale Residual Gain Error (ppm of Reading) Residual Offset Error (ppm of Range) Offset Tempco (ppm of Range/°C) Random Noise, σ (μVrms) Absolute Accuracy at Full Scale (μV) Sensitivity (μV)
10 -10 45 10 11 70 1,050 28.0
5 -5 50 10 11 35 550 14.0
2 -2 50 10 13 15 230 6.0
1 -1 60 17 15 12 130 4.8
0.5 -0.5 60 32 20 10 80 4.0
0.2 -0.2 80 47 35 9 43 3.6
0.1 -0.1 120 62 60 9 31 3.6
Note Sensitivity is the smallest voltage change that can be detected. It is a function of noise.
Table 13. AI Absolute Accuracy Values (Filter Off)
Gain tempco 17 ppm/°C
Reference tempco 1 ppm/°C
INL error 10 ppm of range

AI Absolute Accuracy Equation

AbsoluteAccuracy = Reading · (GainError) + Range · (OffsetError) + NoiseUncertainty

  • GainError = ResidualAIGainError + GainTempco · (TempChangeFromLastInternalCal) + ReferenceTempco · (TempChangeFromLastExternalCal)
  • OffsetError = ResidualAIOffsetError + OffsetTempco · (TempChangeFromLastInternalCal) + INLError
  • NoiseUncertainty =
    Random⁢ Noise⁢ ⋅  3100⁡
    for a coverage factor of 3 σ and averaging 100 points.

AI Absolute Accuracy Example

Absolute accuracy at full scale on the analog input channels is determined using the following assumptions:

  • TempChangeFromLastExternalCal = 10 °C
  • TempChangeFromLastInternalCal = 1 °C
  • number_of_readings = 100
  • CoverageFactor = 3 σ

For example, on the 10 V range of the Filter On accuracy table, the absolute accuracy at full scale is as follows:

  • GainError = 40 ppm + 17 ppm · 1 + 1 ppm · 10 = 67 ppm
  • OffsetError = 8 ppm + 11 ppm · 1 + 10 ppm = 29 ppm
  • NoiseUncertainty =
    60⁢  ⁢µV⁢⋅ 3100
    = 18 µV
  • AbsoluteAccuracy = 10 V · (GainError) + 10 V · (OffsetError) + NoiseUncertainty = 980 µV

Analog Triggers

Table 14. Analog Triggers
Number of triggers 1
Source AI <0..15>, APFI 0
Functions Start Trigger, Reference Trigger, Pause Trigger, Sample Clock, Convert Clock, Sample Clock Timebase
Resolution 10 bits, 1 in 1,024
Modes Analog edge triggering, analog edge triggering with hysteresis, and analog window triggering
Accuracy ±1% of range
Table 15. Source Level
AI <0..15> ±Full scale
APFI 0 ±10 V
Table 16. Bandwidth (-3 dB)
AI <0..15> 700 kHz filter off, 40 kHz filter on
APFI 0 5 MHz
Table 17. APFI 0
Input impedance 10 kΩ
Coupling DC
Protection, power on ±30 V
Protection, power off ±15 V

Analog Output

Table 18. Analog Output
Number of channels 2
DAC resolution 16 bits
DNL ±1 LSB
Monotonicity 16 bit guaranteed
Accuracy Refer to AO Absolute Accuracy
Output coupling DC
Output impedance 0.2 Ω
Output current drive ±5 mA
Output FIFO size 8,191 samples shared among channels used
Table 19. AO Maximum Update Rate
1 channel 2.86 MS/s
2 channels 2.00 MS/s per channel
Table 20. AO Timing
Timing accuracy 50 ppm of sample rate
Timing resolution 50 ns
Table 21. Output Range (Offset ± Reference)
Calibrated ranges ±1 V, ±2 V, ±5 V, ±10 V
Offset sources 0 V, 5 V, APFI 0 , AO <0,1 >[1]1 An AO channel cannot be a reference or offset to itself.
Reference sources 1 V, 5 V, 2 V, 10 V, APFI 0, AO <0,1>[2]2 When the USB Screw Terminal device is powered on, the analog output signal is not defined until after the USB configuration is complete.
Maximum output level ±11 V
Table 22. AO Protection
Overdrive protection ±25 V
Overdrive current 20 mA
Table 23. AO Power-On
Power-on state[3]3 For all USB Screw Terminal devices, when powered on, the analog output signal is not defined until after USB configuration is complete. ±5 mV
Power-on glitch 2.3 V peak for 1.2 s
Table 24. AO Data Transfers
PCI/PXI DMA (scatter-gather), interrupts, programmed I/O
USB USB Signal Stream, programmed I/O
Table 25. AO Waveform Modes and Settling Time
AO waveform modes Non-periodic waveform, periodic waveform regeneration mode from onboard FIFO, periodic waveform regeneration from host buffer including dynamic update
Settling time, full-scale step, 15 ppm (1 LSB) 3 µs
Slew rate 20 V/µs
Table 26. AO Glitch Energy at Midscale Transition, ±10 V Range
Magnitude 15 mV
Duration 0.5 µs

External Reference

Table 27. APFI 0
Input impedance 10 kΩ
Coupling DC
Protection, device on ±30 V
Protection, device off ±15 V
Range ±11 V
Figure 7. AO <0,1> External Reference Bandwidth


AO Absolute Accuracy

Absolute accuracy at full-scale numbers is valid immediately following internal calibration and assumes the device is operating within 10 °C of the last external calibration.

Note Accuracies listed are valid for up to two years from the device external calibration.
Table 28. AO Absolute Accuracy
Nominal Range Positive Full Scale Nominal Range Negative Full Scale Residual Gain Error (ppm of Reading) Gain Tempco (ppm/°C) Residual Offset Error (ppm of Range) Offset Tempco (ppm of Range/°C) Absolute Accuracy at Full Scale (μV)
10 -10 55 15 30 12 1,540
5 -5 60 15 30 17 820
2 -2 65 25 40 30 404
1 -1 85 25 57 50 259
Table 29. AO Absolute Accuracy Values
Reference tempco 1 ppm/°C
INL error 32 ppm of range

AO Absolute Accuracy Equation

AbsoluteAccuracy = OutputValue · (GainError) + Range · (OffsetError)

  • GainError = ResidualGainError + GainTempco · (TempChangeFromLastInternalCal) + ReferenceTempco · (TempChangeFromLastExternalCal)
  • OffsetError = ResidualOffsetError + AOOffsetTempco · (TempChangeFromLastInternalCal) + INLError

Digital I/O/PFI

Static Characteristics

Table 30. Static DIO/PFI Characteristics
Number of channels 24 total, 8 (P0.<0..7>), 16 (PFI <0..7>/P1, PFI <8..15>/P2)
I/O type 5 V TTL/CMOS compatible
Ground reference D GND
Direction control Each terminal individually programmable as input or output
Pull-down resistor 50 kΩ typical, 20 kΩ minimum
Input voltage protection ±20 V on up to two pins[4]4 Stresses beyond those listed under Input voltage protection may cause permanent damage to the device.

Waveform Characteristics (Port 0 Only)

Table 31. DIO Waveform Characteristics (Port 0 Only)
Terminals used Port 0 (P0.<0..7>)
Port/sample size Up to 8 bits
Waveform generation (DO) FIFO 2,047 samples
Waveform acquisition (DI) FIFO 2,047 samples
DI or DO Sample Clock source[5]5 The digital subsystem does not have its own dedicated internal timing engine. Therefore, a sample clock must be provided from another subsystem on the device or an external source. Any PFI, RTSI, AI Sample or Convert Clock, AO Sample Clock, Ctr n Internal Output, and many other signals
Table 32. DI Sample Clock Frequency
PCI/PXI 0 MHz to 10 MHz, system and bus activity dependent
USB 0 MHz to 1 MHz, system and bus activity dependent
Table 33. DO Sample Clock Frequency (PCI/PXI)
Regenerate from FIFO 0 MHz to 10 MHz
Streaming from memory 0 to 10 MHz, system and bus activity dependent
Table 34. DO Sample Clock Frequency (USB)
Regenerate from FIFO 0 MHz to 10 MHz
Streaming from memory 0 MHz to 1 MHz, system and bus activity dependent
Table 35. Data Transfers
PCI/PXI DMA (scatter-gather), interrupts, programmed I/O
USB USB Signal Stream, programmed I/O

PFI/Port 1/Port 2 Functionality

Table 36. PFI/Port 1/Port 2 Functionality
Functionality Static digital input, static digital output, timing input, timing output
Timing output sources Many AI, AO, counter, DI, DO timing signals
Debounce filter settings 125 ns, 6.425 µs, 2.56 ms, disable; high and low transitions; selectable per input

Recommended Operating Conditions

Table 37. Recommended Operating Conditions
Level Minimum Maximum
Input high voltage (VIH) 2.2 V 5.25 V
Input low voltage (VIL) 0 V 0.8 V
Output high current (IOH) P0.<0..7> — -24 mA
Output high current (IOH) PFI <0..15>/P1/P2 — -16 mA
Output low current (IOL) P0.<0..7> — 24 mA
Output low current (IOL) PFI <0..15>/P1/P2 — 16 mA

Electrical Characteristics

Table 38. Electrical Characteristics
Level Minimum Maximum
Positive-going threshold (VT+) — 2.2 V
Negative-going threshold (VT-) 0.8 V —
Delta VT hysteresis (VT+ - VT-) 0.2 V —
IIL input low current (Vin = 0 V) — -10 µA
IIH input high current (Vin = 5 V) — 250 µA

Digital I/O Characteristics

Figure 8. Digital I/O (P0.<0..7>): Ioh versus Voh


Figure 9. Digital I/O (PFI <0..15>/P1/P2): Ioh versus Voh


Figure 10. Digital I/O (P0.<0..7>): Iol versus Vol


Figure 11. Digital I/O (PFI <0..15>/P1/P2): Iol versus Vol


General-Purpose Counters/Timers

Table 39. General-Purpose Counters/Timer
Number of counter/timers 2
Resolution 32 bits
Counter measurements Edge counting, pulse, semi-period, period, two-edge separation
Position measurements X1, X2, X4 quadrature encoding with Channel Z reloading; two-pulse encoding
Output applications Pulse, pulse train with dynamic updates, frequency division, equivalent time sampling
Internal base clocks 80 MHz, 20 MHz, 0.1 MHz
External base clock frequency 0 MHz to 20 MHz
Base clock accuracy 50 ppm
Inputs Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down
Routing options for inputs Any PFI, RTSI, PXI_TRIG, PXI_STAR, analog trigger, many internal signals
FIFO 2 samples
Table 40. Counter/Timer Data Transfers
PCI/PXI Dedicated scatter-gather DMA controller for each counter/timer; interrupts, programmed I/O
USB USB Signal Stream, programmed I/O

Frequency Generator

Table 41. Frequency Generator
Number of channels 1
Base clocks 10 MHz, 100 kHz
Divisors 1 to 16
Base clock accuracy 50 ppm

Output can be available on any output PFI or RTSI terminal.

Phase-Locked Loop (PLL) (PCI/PXI Only)

Table 42. PLL
Number of PLLs 1
Reference signal PXI_STAR, PXI_CLK10, RTSI <0..7>
Output of PLL 80 MHz Timebase; other signals derived from 80 MHz Timebase including 20 MHz and 100 kHz Timebases

External Digital Triggers

Table 43. External Digital Triggers
Source Any PFI, RTSI, PXI_TRIG, PXI_STAR
Polarity Software-selectable for most signals
Analog input function Start Trigger, Reference Trigger, Pause Trigger, Sample Clock, Convert Clock, Sample Clock Timebase
Analog output function Start Trigger, Pause Trigger, Sample Clock, Sample Clock Timebase
Counter/timer function Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down
Digital waveform generation (DO) function Sample Clock
Digital waveform acquisition (DI) function Sample Clock

Device-to-Device Trigger Bus

Table 44. Device-to-Device Trigger Bus
PCI RTSI <0..7>[6]6 In other sections of this document, RTSI refers to RTSI <0..7> for the PCI devices or PXI_TRIG <0..7> for PXI devices.
PXI PXI_TRIG <0..7>, PXI_STAR
USB source None
Output selections 10 MHz Clock, frequency generator output, many internal signals
Debounce filter settings 125 ns, 6.425 μs, 2.56 ms, disable; high and low transitions; selectable per input

Bus Interface

Table 45. Bus Interface
PCI/PXI 3.3 V or 5 V signal environment
USB USB 2.0 Hi-Speed or full-speed[7]7 If you are using an USB M Series device in full-speed mode, device performance will be lower and you will not be able to achieve maximum sample/update rates., [8]8 Operating on a full-speed bus may result in lower performance.
DMA channels (PCI/PXI) 6, can be used for analog input, analog output, digital input, digital output, counter/timer 0, counter/timer 1
USB Signal Stream 4, can be used for analog input, analog output, digital input, digital output, counter/timer 0, counter/timer 1
The PXI device supports one of the following features:
  • May be installed in PXI Express hybrid slots
  • Or, may be used to control SCXI in PXI/SCXI combo chassis
Table 46. PXI/SCXI Combo and PXI Express Chassis Compatibility
M Series Part Number SCXI Control in PXI/SCXI Combo Chassis PXI Express Hybrid Slot Compatible
191501C-03 No Yes
191501A-0x/191501B-0x Yes No

Power Requirements

Table 47. Current Draw from Bus During No-Load Condition (PCI/PXI)
+5 V 0.03 A
+3.3 V 0.78 A
+12 V 0.40 A
-12 V 0.06 A
Table 48. Current Draw from Bus During AI and AO Overvoltage Condition (PCI/PXI)
+5 V 0.03 A
+3.3 V 1.26 A
+12 V 0.43 A
-12 V 0.06 A
Note Current draw from bus during no-load condition or AI/AO overvoltage condition does not include P0/PFI/P1/P2 and +5 V terminals.
Caution USB devices must be powered with an NI offered AC adapter or a National Electric Code (NEC) Class 2 DC source that meets the power requirements for the device and has appropriate safety certification marks for country of use.
Table 49. USB Power Supply Requirements
USB power supply requirements 11 to 30 VDC, 20 W, locking or non-locking power jack with 0.080 in. diameter center pin, 5/16-32 thread for locking collars
USB power supply fuse 2 A, 250 V

Current Limits

Caution Exceeding the current limits may cause unpredictable behavior by the device and/or PC/chassis.
Table 50. PCI Current Limits
+5 V terminal 1 A maximum
Note The +5 V terminal on older PCI/PXI board revisions has a self-resetting fuse that opens when current exceeds this specification. Newer revisions have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.
Table 51. PXI Current Limits
+5 V terminal 1 A maximum
P0/PFI/P1/P2 and +5 V terminals combined 2 A maximum
Note The +5 V terminal on older PCI/PXI board revisions has a self-resetting fuse that opens when current exceeds this specification. Newer revisions have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.
Table 52. USB Current Limits
+5 V terminal 1 A maximum
P0/PFI/P1/P2 and +5 V terminals combined 2 A maximum
Note The USB-6281 has a user-replaceable socketed fuse that opens when current exceeds this specification. Refer to the M Series User Manual for information about fuse replacement.

Physical Characteristics

Table 53. Dimensions
PCI printed circuit board 10.6 cm × 15.5 cm (4.2 in. × 6.1 in.)

For more information, visit ni.com/dimensions and search by module number.
PXI printed circuit board Standard 3U PXI

For more information, visit ni.com/dimensions and search by module number.
Mass Termination enclosure (includes connectors) 18.8 cm × 17.09 cm × 4.45 cm (7.4 in. × 6.73 in. × 1.75 in.)
Screw Terminal (includes connectors) 26.67 cm × 17.09 cm × 4.45 cm (10.5 in. × 6.73 in. × 1.75 in.)
USB OEM Refer to the NI USB-622x/625x/628x OEM User Guide
Table 54. Weight
PCI 158 g (5.6 oz)
PXI 225 g (7.9 oz)
USB Mass Termination 1.04 kg (2 lb 4.5 oz)
USB Screw Terminal 1.46 kg (3 lb 3.4 oz)
USB OEM 261 g (9.2 oz)
Table 55. I/O Connectors
PCI/PXI 1 68-pin VHDCI
USB Mass Termination 1 68-pin SCSI
USB Screw Terminal 64 screw terminals
USB OEM 1 34-pin IDC, 1 50-pin IDC
Table 56. Screw Terminal Wiring
Screw terminal wiring 16 AWG to 28 AWG

Calibration

Table 57. Calibration
PCI/PXI/PCI Express/PXI Express recommended warm-up time 15 minutes
USB recommended warm-up time 30 minutes
Calibration interval 2 years

Maximum Working Voltage

Connect only voltages that are below these limits.

Table 58. Maximum Working Voltage
Channel-to-earth 11 V, Measurement Category I

Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage. MAINS is a hazardous live electrical supply system that powers equipment. This category is for measurements of voltages from specially protected secondary circuits. Such voltage measurements include signal levels, special equipment, limited-energy parts of equipment, circuits powered by regulated low-voltage sources, and electronics.

Caution Do not use for measurements within Categories II, III, or IV.
Note Measurement Categories CAT I and CAT O (Other) are equivalent. These test and measurement circuits are not intended for direct connection to the MAINS building installations of Measurement Categories CAT II, CAT III, or CAT IV.

Environmental

Table 59. Environmental Characteristics
PCI/PXI operating temperature 0 ºC to 55 ºC
USB operating temperature 0 ºC to 45 ºC
Storage temperature -20 ºC to 70 ºC
Humidity 10% RH to 90% RH, noncondensing
Maximum altitude 2,000 m
Pollution Degree 2
Indoor use only.

Shock and Vibration (PXI Only)

Table 60. Shock and Vibration
Operational shock 30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.)
Random vibration, operating 5 Hz to 500 Hz, 0.3 grms
Random vibration, nonoperating 5 Hz to 500 Hz, 2.4 grms (Tested in accordance with IEC 60068-2-64. Nonoperating test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

Safety Compliance Standards

This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

  • IEC 61010-1, EN 61010-1
  • UL 61010-1, CSA C22.2 No. 61010-1
Note For safety certifications, refer to the product label or the Product Certifications and Declarations section.

EMC Standards

This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:

  • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
  • EN 55011 (CISPR 11): Group 1, Class A emissions
  • EN 55022 (CISPR 22): Class A emissions
  • EN 55024 (CISPR 24): Immunity
  • AS/NZS CISPR 11: Group 1, Class A emissions
  • AS/NZS CISPR 22: Class A emissions
  • FCC 47 CFR Part 15B: Class A emissions
  • ICES-001: Class A emissions
Note In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia and New Zealand (per CISPR 11) Class A equipment is intended for use only in heavy-industrial locations.
Note Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.
Note For EMC declarations and certifications, and additional information, refer to the Product Certifications and Declarations section.

1 An AO channel cannot be a reference or offset to itself.

2 When the USB Screw Terminal device is powered on, the analog output signal is not defined until after the USB configuration is complete.

3 For all USB Screw Terminal devices, when powered on, the analog output signal is not defined until after USB configuration is complete.

4 Stresses beyond those listed under Input voltage protection may cause permanent damage to the device.

5 The digital subsystem does not have its own dedicated internal timing engine. Therefore, a sample clock must be provided from another subsystem on the device or an external source.

6 In other sections of this document, RTSI refers to RTSI <0..7> for the PCI devices or PXI_TRIG <0..7> for PXI devices.

7 If you are using an USB M Series device in full-speed mode, device performance will be lower and you will not be able to achieve maximum sample/update rates.

8 Operating on a full-speed bus may result in lower performance.