PCI/PXI-6224 Specifications

PCI/PXI-6224 Specifications

These specifications apply to the PCI-6224 and PXI-6224 models.

The following specifications are typical at 25 °C, unless otherwise noted.

Revision History

Version Date changed Description
375202E-01 November 2025 Updated I/O connector specifications.
375202D-01 June 2025 Added pinout diagrams.
375202C-01 June 2016 Updated formatting.
375202B-01 September 2015 Updated formatting.
375202A-01 July 2015 Initial release.
371290G-01 April 2009 Original specifications document: NI 622x Specifications.

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Definitions

Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

  • Typical specifications describe the performance met by a majority of models.
  • Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.

Specifications are Typical unless otherwise noted.

PCI/PXI-6224 Pinout



Analog Input

Table 1. Analog Input
Number of channels 16 differential or 32 single ended
ADC resolution 16 bits
DNL No missing codes guaranteed
INL Refer to AI Absolute Accuracy
Timing accuracy 50 ppm of sample rate
Timing resolution 50 ns
Input coupling DC
Input range ±0.2 V, ±1 V, ±5 V, ±10 V
Maximum working voltage for analog inputs (signal + common mode) ±11 V of AI GND
CMRR (DC to 60 Hz) 92 dB
Input bias current ±100 pA
Small signal bandwidth (-3 dB) 700 kHz
Input FIFO size 4,095 samples
Scan list memory 4,095 entries
Table 2. AI Sample Rate
Single channel maximum 250 kS/s
Multichannel maximum (aggregate) 250 kS/s
Minimum No minimum
Data transfers DMA (scatter-gather), interrupts, programmed I/O
Table 3. AI Input Impedance
Device on, AI+ to AI GND >10 GΩ in parallel with 100 pF
Device on, AI- to AI GND >10 GΩ in parallel with 100 pF
Device off, AI+ to AI GND 820 Ω
Device off, AI- to AI GND 820 Ω
Table 4. AI Crosstalk (at 100 kHz)
Adjacent channels -75 dB
Non-adjacent channels -90 dB
Table 5. AI Overvoltage Protection for All Analog Input and Sense Channels
Device on ±25 V for up to two AI pins
Device off ±15 V for up to two AI pins
Table 6. AI Input Current During Overvoltage Condition
Input current during overvoltage condition ±20 mA maximum/AI pin

Settling Time for Multichannel Measurements

Table 7. Accuracy, Full-Scale Step, All Ranges
±90 ppm of step (±6 LSB) 4 μs convert interval
±30 ppm of step (±2 LSB) 5 μs convert interval
±15 ppm of step (±1 LSB) 7 μs convert interval

Typical Performance Graphs

Figure 1. Settling Error versus Time for Different Source Impedances


Figure 2. AI Small Signal Bandwidth


Figure 3. AI CMRR


AI Absolute Accuracy

Note Accuracies listed are valid for up to one year from the device external calibration.
Table 8. AI Absolute Accuracy
Nominal Range Positive Full Scale Nominal Range Negative Full Scale Residual Gain Error (ppm of Reading) Residual Offset Error (ppm of Range) Offset Tempco (ppm of Range/°C) Random Noise, σ (μVrms) Absolute Accuracy at Full Scale (μV) Sensitivity (μV)
10 -10 75 20 57 244 3,100 97.6
5 -5 85 20 60 122 1,620 48.8
1 -1 95 25 79 30 360 12.0
0.2 -0.2 135 80 175 13 112 5.2
Note Sensitivity is the smallest voltage change that can be detected. It is a function of noise.
Table 9. AI Absolute Accuracy Values
Gain tempco 25 ppm/°C
Reference tempco 5 ppm/°C
INL error 76 ppm of range

AI Absolute Accuracy Equation

AbsoluteAccuracy = Reading · (GainError) + Range · (OffsetError) + NoiseUncertainty

  • GainError = ResidualAIGainError + GainTempco · (TempChangeFromLastInternalCal) + ReferenceTempco · (TempChangeFromLastExternalCal)
  • OffsetError = ResidualAIOffsetError + OffsetTempco · (TempChangeFromLastInternalCal) + INLError
  • NoiseUncertainty =
    RandomNoise3100
    for a coverage factor of 3 σ and averaging 100 points.

AI Absolute Accuracy Example

Absolute accuracy at full scale on the analog input channels is determined using the following assumptions:

  • TempChangeFromLastExternalCal = 10 °C
  • TempChangeFromLastInternalCal = 1 °C
  • number_of_readings = 100
  • CoverageFactor = 3 σ

For example, on the 10 V range, the absolute accuracy at full scale is as follows:

  • GainError = 75 ppm + 25 ppm · 1 + 5 ppm · 10 = 150 ppm
  • OffsetError = 20 ppm + 57 ppm · 1 + 76 ppm = 153 ppm
  • NoiseUncertainty =
    244µV3100
    = 73 µV
  • AbsoluteAccuracy = 10 V · (GainError) + 10 V · (OffsetError) + NoiseUncertainty = 3,100 µV

Digital I/O and PFI

Static Characteristics

Table 10. Static DIO/PFI Characteristics
Number of channels 48 total, 32 (P0.<0..31>), 16 (PFI <0..7>/P1, PFI <8..15>/P2)
Ground reference D GND
Direction control Each terminal individually programmable as input or output
Pull-down resistor 50 kΩ typical, 20 kΩ minimum
Input voltage protection ±20 V on up to two pins[1]1 Stresses beyond those listed under Input voltage protection may cause permanent damage to the device.

Waveform Characteristics (Port 0 Only)

Table 11. DIO Waveform Characteristics (Port 0 Only)
Terminals used Port 0 (P0.<0..31>)
Port/sample size Up to 32 bits
Waveform generation (DO) FIFO 2,047 samples
Waveform acquisition (DI) FIFO 2,047 samples
DI or DO Sample Clock source[2]2 The digital subsystem does not have its own dedicated internal timing engine. Therefore, a sample clock must be provided from another subsystem on the device or an external source. Any PFI, RTSI, AI Sample or Convert Clock, Ctr n Internal Output, and many other signals
DI or DO Sample Clock frequency 0 MHz to 1 MHz, system and bus activity dependent
Data transfers DMA (scatter-gather), interrupts, programmed I/O

PFI/Port 1/Port 2 Functionality

Table 12. PFI/Port 1/Port 2 Functionality
Functionality Static digital input, static digital output, timing input, timing output
Timing output sources Many AI, counter, DI, DO timing signals
Debounce filter settings 125 ns, 6.425 µs, 2.56 ms, disable; high and low transitions; selectable per input

Recommended Operating Conditions

Table 13. PCI/PXI
Level Minimum Maximum
Input high voltage (VIH) 2.2 V 5.25 V
Input low voltage (VIL) 0 V 0.8 V
Output high current (IOH) P0.<0..31> -24 mA
Output high current (IOH) PFI <0..15>/P1/P2 -16 mA
Output low current (IOL) P0.<0..31> 24 mA
Output low current (IOL) PFI <0..15>/P1/P2 -— 16 mA

Electrical Characteristics

Table 14. Electrical Characteristics
Level Minimum Maximum
Positive-going threshold (VT+) 2.2 V
Negative-going threshold (VT-) 0.8 V
Delta VT hysteresis (VT+ - VT-) 0.2 V
IIL input low current (Vin = 0 V) -10 µA
IIH input high current (Vin = 5 V) 250 µA

Digital I/O Characteristics

Figure 4. DIO (P0.<0..31>): Ioh versus Voh


Figure 5. DIO (PFI <0..15>/P1/P2): Ioh versus Voh


Figure 6. DIO (P0.<0..31>): Iol versus Vol


Figure 7. DIO (PFI <0..15>/P1/P2): Iol versus Vol


General-Purpose Counters/Timers

Table 15. General-Purpose Counters/Timer
Number of counter/timers 2
Resolution 32 bits
Counter measurements Edge counting, pulse, semi-period, period, two-edge separation
Position measurements X1, X2, X4 quadrature encoding with Channel Z reloading; two-pulse encoding
Output applications Pulse, pulse train with dynamic updates, frequency division, equivalent time sampling
Internal base clocks 80 MHz, 20 MHz, 0.1 MHz
External base clock frequency 0 MHz to 20 MHz
Base clock accuracy 50 ppm
Inputs Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down
Routing options for inputs Any PFI, RTSI, PXI_TRIG, PXI_STAR, analog trigger, many internal signals
FIFO 2 samples
Data transfers Dedicated scatter-gather DMA controller for each counter/timer; interrupts; programmed I/O

Frequency Generator

Table 16. Frequency Generator
Number of channels 1
Base clocks 10 MHz, 100 kHz
Divisors 1 to 16
Base clock accuracy 50 ppm

Output can be available on any output PFI or RTSI terminal.

Phase-Locked Loop (PLL)

Table 17. PLL
Number of PLLs 1
Reference signal PXI_STAR, PXI_CLK10, RTSI <0..7>
Output of PLL 80 MHz Timebase; other signals derived from 80 MHz Timebase including 20 MHz and 100 kHz Timebases

External Digital Triggers

Table 18. External Digital Triggers
Source Any PFI, RTSI, PXI_TRIG, PXI_STAR
Polarity Software-selectable for most signals
Analog input function Start Trigger, Reference Trigger, Pause Trigger, Sample Clock, Convert Clock, Sample Clock Timebase
Counter/timer function Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down
Digital waveform generation (DO) function Sample Clock
Digital waveform acquisition (DI) function Sample Clock

Device-to-Device Trigger Bus

Table 19. Device-to-Device Trigger Bus
PCI RTSI <0..7>[3]3 In other sections of this document, RTSI refers to RTSI <0..7> for the PCI devices or PXI_TRIG <0..7> for PXI devices.
PXI PXI_TRIG <0..7>, PXI_STAR
Output selections 10 MHz Clock, frequency generator output, many internal signals
Debounce filter settings 125 ns, 6.425 μs, 2.56 ms, disable; high and low transitions; selectable per input

Bus Interface

Table 20. Bus Interface
PCI/PXI 3.3 V or 5 V signal environment
DMA channels 6, can be used for analog input, digital input, digital output, counter/timer 0, counter/timer 1

The PXI device supports one of the following features:

  • May be installed in PXI Express hybrid slots
  • Or, may be used to control SCXI in PXI/SCXI combo chassis
Table 21. PXI/SCXI Combo and PXI Express Chassis Compatibility
M Series Part Number SCXI Control in PXI/SCXI Combo Chassis PXI Express Hybrid Slot Compatible
191332B-02 No Yes
191322A-0x Yes No

Power Requirements

Table 22. PCI/PXI Current Draw from Bus During No-Load Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+5 V 0.02 A
+3.3 V 0.25 A
+12 V 0.15 A
Table 23. PCI/PXI Current Draw from Bus During AI and AO Overvoltage Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+5 V 0.02 A
+3.3 V 0.25 A
+12 V 0.25 A

Current Limits

Caution Exceeding the current limits may cause unpredictable behavior by the device and/or PC/chassis.
Table 24. PCI Current Limits
+5 V terminal (connector 0) 1 A maximum. See note.
+5 V terminal (connector 1) 1 A maximum. See note.
Note Older revisions of the PCI device have a self-resetting fuse that opens when current exceeds the current limit on the +5 V terminal. Newer revisions of the device have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.
Table 25. PXI Current Limits
+5 V terminal (connector 0) 1 A maximum. See note.
+5 V terminal (connector 1) 1 A maximum. See note.
P0/PFI/P1/P2 and +5 V terminals combined 2 A maximum
Note Older revisions of the PXI module have a self-resetting fuse that opens when current exceeds the current limit on the +5 V terminal. Newer revisions of the module have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.

Physical Characteristics

Table 26. Dimensions
PCI-6224 printed circuit board 10.6 cm × 15.5 cm (4.2 in. × 6.1 in.)
PXI-6224 printed circuit board Standard 3U PXI
Table 27. Weight
PCI-6224 99 g (3.5 oz)
PXI-6224 170 g (5.9 oz)
Table 28. I/O Connectors
I/O connectors 2 68-pin VHDCI

Calibration

You can obtain the calibration certificate and information about calibration services for the PCI/PXI-6224 at ni.com/calibration.

Table 29. Calibration
Recommended warm-up time 15 minutes
Calibration interval 1 year

Maximum Working Voltage

Connect only voltages that are below these limits.

Table 30. Maximum Working Voltage
Channel-to-earth 11 V, Measurement Category I

Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage. MAINS is a hazardous live electrical supply system that powers equipment. This category is for measurements of voltages from specially protected secondary circuits. Such voltage measurements include signal levels, special equipment, limited-energy parts of equipment, circuits powered by regulated low-voltage sources, and electronics.

Caution Do not use for measurements within Categories II, III, or IV.
Note Measurement Categories CAT I and CAT O (Other) are equivalent. These test and measurement circuits are not intended for direct connection to the MAINS building installations of Measurement Categories CAT II, CAT III, or CAT IV.

Environmental

Table 31. Temperature
Operating 0 ºC to 55 ºC
Storage -20 ºC to 70 ºC
Table 32. Humidity
Humidity 10% RH to 90% RH, noncondensing
Table 33. Pollution Degree
Pollution Degree 2
Table 34. Maximum Altitude
Maximum altitude 2,000 m

Indoor use only.

Shock and Vibration (PXI Only)

Table 35. Shock and Vibration
Operational shock 30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.)
Random vibration, operating 5 Hz to 500 Hz, 0.3 grms
Random vibration, nonoperating 5 Hz to 500 Hz, 2.4 grms (Tested in accordance with IEC 60068-2-64. Nonoperating test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

Safety Compliance Standards

This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

  • IEC 61010-1, EN 61010-1
  • UL 61010-1, CSA C22.2 No. 61010-1
Note For safety certifications, refer to the product label or the Product Certifications and Declarations section.

EMC Standards

This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:

  • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
  • EN 55011 (CISPR 11): Group 1, Class A emissions
  • EN 55022 (CISPR 22): Class A emissions
  • EN 55024 (CISPR 24): Immunity
  • AS/NZS CISPR 11: Group 1, Class A emissions
  • AS/NZS CISPR 22: Class A emissions
  • FCC 47 CFR Part 15B: Class A emissions
  • ICES-001: Class A emissions
Note In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia and New Zealand (per CISPR 11) Class A equipment is intended for use only in heavy-industrial locations.
Note Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.
Note For EMC declarations and certifications, and additional information, refer to the Product Certifications and Declarations section.

CE Compliance

This product meets the essential requirements of applicable European Directives, as follows:

  • 2014/35/EU; Low-Voltage Directive (safety)
  • 2014/30/EU; Electromagnetic Compatibility Directive (EMC)
  • 2011/65/EU; Restriction of Hazardous Substances (RoHS)

Product Certifications and Declarations

Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit ni.com/product-certifications, search by model number, and click the appropriate link.

Environmental Management

NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

For additional environmental information, refer to the Engineering a Healthy Planet web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

EU and UK Customers

  • Waste Electrical and Electronic Equipment (WEEE)—At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.
  • 电子信息产品污染控制管理办法(中国RoHS)

  • 中国RoHSNI符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于NI中国RoHS合规性信息,请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)
  • 1 Stresses beyond those listed under Input voltage protection may cause permanent damage to the device.

    2 The digital subsystem does not have its own dedicated internal timing engine. Therefore, a sample clock must be provided from another subsystem on the device or an external source.

    3 In other sections of this document, RTSI refers to RTSI <0..7> for the PCI devices or PXI_TRIG <0..7> for PXI devices.