IMAQ FPGA Flat Field Correction VI
- Updated2023-02-21
- 21 minute(s) read
Requires: NI Vision Development Module FPGA
Corrects image intensity using flat field and dark field images and returns a corrected image.
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Note
The x8 VI instances have variable latency. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency. Total Latency = Minimum Latency + 1 |
IMAQ FPGA Flat Field Correction U8 x1
Corrects image intensity using flat field and dark field images and returns a corrected image. Recreate the flat field image whenever the imaging setup changes. Transfer the flat field image from the host using DMA or use the IMAQ FPGA Generate Flat Field Image VI to create the image for the Flat Field Pixel Bus In input. Use the IMAQ Flat Field Parameters VI to compute the Median input.
Supported Image Types
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Correction Factor is used to bias the mean computed from the flat field image. Typically this parameter ranges from 1 to 1.5. Increasing this value will brighten the corrected image. |
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Median is the median image resulting from subtracting the dark field image from the flat field image. |
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Flat Field Pixel Bus In is a flat field image used to correct Pixel Bus In.
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Dark Field Pixel Bus In is a dark field image used to correct Pixel Bus In. You can create a dark field image by covering the camera lens and capturing an image.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Flat Field Correction U8 x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 843
- Slice LUTs: 988
- DSP48s: 2
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 23
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 858
- Slice LUTs: 987
- DSP48s: 3
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 23
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 894
- Slice LUTs: 803
- DSP48s: 2
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 23
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 863
- Slice LUTs: 852
- DSP48s: 2
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 23
- Initiation Interval: 1
IMAQ FPGA Flat Field Correction U8 x8
Corrects image intensity using flat field and dark field images and returns a corrected image. Recreate the flat field image whenever the imaging setup changes. Transfer the flat field image from the host using DMA or use the IMAQ FPGA Generate Flat Field Image VI to create the image for the Flat Field Pixel Bus In input. Use the IMAQ Flat Field Parameters VI to compute the Median input.
Supported Image Types
|
Correction Factor is used to bias the mean computed from the flat field image. Typically this parameter ranges from 1 to 1.5. Increasing this value will brighten the corrected image. |
||||||||||
|
Median is the median image resulting from subtracting the dark field image from the flat field image. |
||||||||||
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Flat Field Pixel Bus In is a flat field image used to correct Pixel Bus In.
|
||||||||||
|
Dark Field Pixel Bus In is a dark field image used to correct Pixel Bus In. You can create a dark field image by covering the camera lens and capturing an image.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Flat Field Correction U8 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 4318
- Slice LUTs: 5759
- DSP48s: 9
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA Flat Field Correction U16 x1
Corrects image intensity using flat field and dark field images and returns a corrected image. Recreate the flat field image whenever the imaging setup changes. Transfer the flat field image from the host using DMA or use the IMAQ FPGA Generate Flat Field Image VI to create the image for the Flat Field Pixel Bus In input. Use the IMAQ Flat Field Parameters VI to compute the Median input.
Supported Image Types
|
Correction Factor is used to bias the mean computed from the flat field image. Typically this parameter ranges from 1 to 1.5. Increasing this value will brighten the corrected image. |
||||||||||
 |
Median is the median image resulting from subtracting the dark field image from the flat field image. |
||||||||||
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Flat Field Pixel Bus In is a flat field image used to correct Pixel Bus In.
|
||||||||||
|
Dark Field Pixel Bus In is a dark field image used to correct Pixel Bus In. You can create a dark field image by covering the camera lens and capturing an image.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Flat Field Correction U16 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1667
- Slice LUTs: 2110
- DSP48s: 3
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 29
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1665
- Slice LUTs: 2193
- DSP48s: 3
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 29
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 2062
- Slice LUTs: 1825
- DSP48s: 3
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 38
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1830
- Slice LUTs: 1620
- DSP48s: 3
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 38
- Initiation Interval: 1
IMAQ FPGA Flat Field Correction U16 x8
Corrects image intensity using flat field and dark field images and returns a corrected image. Recreate the flat field image whenever the imaging setup changes. Transfer the flat field image from the host using DMA or use the IMAQ FPGA Generate Flat Field Image VI to create the image for the Flat Field Pixel Bus In input. Use the IMAQ Flat Field Parameters VI to compute the Median input.
Supported Image Types
|
Correction Factor is used to bias the mean computed from the flat field image. Typically this parameter ranges from 1 to 1.5. Increasing this value will brighten the corrected image. |
||||||||||
|
Median is the median image resulting from subtracting the dark field image from the flat field image. |
||||||||||
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Flat Field Pixel Bus In is a flat field image used to correct Pixel Bus In.
|
||||||||||
|
Dark Field Pixel Bus In is a dark field image used to correct Pixel Bus In. You can create a dark field image by covering the camera lens and capturing an image.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Flat Field Correction U16 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 9228
- Slice LUTs: 13507
- DSP48s: 17
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 21
- Initiation Interval: 1
Examples
Refer to the following for an example that uses this VI.
- LabVIEW\examples\Vision FPGA\Flat Field Correction