NI Vision for LabVIEW

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IMAQ FPGA Generate Flat Field Image VI

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  • Updated2023-02-21
  • 10 minute(s) read
Owning Palette: Processing
Requires: NI Vision Development Module FPGA

Generates a flat field image in the FPGA target using the coefficients sent from the host.

Examples

IMAQ FPGA Generate Flat Field Image U8 x1

Generates a flat field image in the FPGA target using the coefficients sent from the host. Use the Estimation instance of the IMAQ Flat Field Parameters VI to generate the Coefficients input.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Generate Flat Field Image U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Coefficients is a cluster of options used to construct the flat field image.

cfxp.gif

Coefficient specifies the polynomial coefficients used to construct the flat field image.
cnclst.gif

Image Size specifies the image width and height in pixels.

cu32.gif

Width is the width of the image in pixels.

cu32.gif

Height is the height of the image in pixels.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.
cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

icclst.gif

Flat Field Pixel Bus Out is the generated flat field image.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.
ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Generate Flat Field Image U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 5933
  • Slice LUTs: 13916
  • DSP48s: 20
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 46
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 5947
  • Slice LUTs: 8345
  • DSP48s: 60
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 46
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 7186
  • Slice LUTs: 8436
  • DSP48s: 36
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 54
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 6859
  • Slice LUTs: 8128
  • DSP48s: 36
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 54
  • Initiation Interval: 1

IMAQ FPGA Generate Flat Field Image U16 x1

Generates a flat field image in the FPGA target using the coefficients sent from the host. Use the Estimation instance of the IMAQ Flat Field Parameters VI to generate the Coefficients input.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Generate Flat Field Image U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Coefficients is a cluster of options used to construct the flat field image.

cfxp.gif

Coefficient specifies the polynomial coefficients used to construct the flat field image.
cnclst.gif

Image Size specifies the image width and height in pixels.

cu32.gif

Width is the width of the image in pixels.

cu32.gif

Height is the height of the image in pixels.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.
cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

icclst.gif

Flat Field Pixel Bus Out is the generated flat field image.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.
ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Generate Flat Field Image U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 7013
  • Slice LUTs: 16760
  • DSP48s: 20
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 47
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 5928
  • Slice LUTs: 8371
  • DSP48s: 60
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 47
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 7029
  • Slice LUTs: 8373
  • DSP48s: 54
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 50
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 6702
  • Slice LUTs: 8026
  • DSP48s: 54
  • Block RAMs: 0

Estimated Performance

  • Minimum Latency: 50
  • Initiation Interval: 1

Examples

Refer to the following for an example that uses this VI.

  • LabVIEW\examples\Vision FPGA\Flat Field Correction

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