NI-SmartNIC is designed to work with PXI Ethernet Interface Modules, such as the PXIe-8290, enabling seamless integration with system-level workflows and build environments.

This section provides an overview of how NI-SmartNIC operates with PXI Ethernet Interface Modules, such as the PXIe-8290. The driver facilitates communication between the host system and the module, enabling configuration, data transfer, and control.

The following sections outline a typical development and deployment workflow using the PXIe-8290 as a representative example. Adapted from the PXIe-8290 User Manual, they demonstrate how NI-SmartNIC integrates with LabVIEW, Vivado, and the included RDMA streaming example. The content walks through the process from FPGA design through compilation and deployment, and explains how the driver interacts with system components like the NIC and host software.

Together, these examples provide a practical foundation for understanding how the driver is used in real-world development scenarios and how the driver interfaces with the PXIe-8290 module.

PXIe-8290 Development Workflow

The PXIe-8290 workflow resembles many NI FlexRIO and/or High-Speed Serial devices, like the PXIe-6593, PXIe-6594, or PXIe-7903. However, the workflow for PXIe-8290 requires exporting the LabVIEW project to Vivado to finish out the compile workflow. You can perform this process by clicking Generate Intermediate Files for the top level LabVIEW FPGA Module VI in the LabVIEW project.

The PXIe-8290 Aurora RDMA Streaming LabVIEW example installs with the NI-SmartNIC driver. The example includes VHDL source files and timing constraints. The files and constraints are necessary for implementing the Aurora protocol within an I/O Socket CLIP. This CLIP is preconfigured to work seamlessly with PXIe-5842, PXIe-7903, and PXIe-7902 modules. For most users, the provided implementation works out of the box. However, if you must customize the Aurora protocol, then you must also modify the VHDL template accordingly.

Compiling the FPGA design for the PXIe-8290 requires exporting the project to Vivado. Once exported, you must manually copy the generated bitfile back into your LabVIEW project. Compiling for the PXIe-8290 outlines this process. Note that the process requires a valid Vivado license and direct interaction with the Vivado design environment.

The PXIe-8290 includes a Mellanox NIC that uses the standard NVIDIA driver that is installed automatically with NI-SmartNIC. The NIC appears in Hardware Configuration Utility, but its configuration is managed directly by the operating system. To change IP settings on Windows, navigate to Settings » Network & Internet » Ethernet. Locate the appropriate NIC (for example, “Mellanox ConnectX-6”), and select Edit. You can identify the correct NIC by its MAC address. You can find the MAC address in Hardware Configuration Utility.

On the server side, an RDMA-capable ConnectX NIC is required to support the streaming rates used in the application. The server must run software that configures its RDMA NIC. The server also routes data through its RDMA NIC before initiating the Aurora data stream. An example RDMA server implementation is included with the NI-SmartNIC driver and installs into the LabVIEW directory.

Compiling for the PXIe-8290

Before you begin:
  • Install the latest release of LabVIEW and LabVIEW FPGA (2025 or later) onto the development machine.
  • Install the latest release of NI-SmartNIC onto the development machine.
  • Download version 2024.1 of Vivado (for example, from the Xilinx website), and install the software onto a separate Linux system for compilation.
  • Install the following Vivado patches to achieve proper FPGA compilation and ensure data integrity.
    • AR000036603 - Versal - Aurora 64B66B IP shows unstable CHANNEL_UP behavior when reset is applied
    • AR000036609 - Vivado 2024.1 - Difference in Vivado generated PLM in BD Flow and DCP Flow
    • AR000036956 - Vivado Synthesis 2024.1 - Crash during Boundary Optimization
    You can find these patches by searching their AR numbers on the AMD Adaptive SoC & FPGA Support portal, or through the links provided in the Related Information panel.
Note This guide assumes that the Vivado tools are installed onto a remotely connected Linux system. The system must have the appropriate Vivado license from Xilinx.
To compile for the PXIe-8290, complete the following steps:
  1. Set up and complete a LabVIEW FPGA Module design with the PXIe-8290.
  2. Export the intermediate design files from the LabVIEW FPGA Module.
    1. Leave the Allow removal of enable signals checkbox unchecked.
    2. If Xilinx Options appear in the build specification settings, you can ignore them.
      Note These options might not be visible in recent versions of the LabVIEW FPGA Module.
    3. Do not to build the FPGA with the cloud compile service.
  3. Copy the intermediate design files onto the Vivado-configured remote system.
    Note Skip this step if you are using Vivado locally.
  4. Use the NI-provided *.tcl compile script on the Vivado-configured remote system, or run an equivalent locally.
    1. Set up the environment for Vivado version 2024.1 by running source /opt/Xilinx/Vivado/2024.1/settings64.sh.
    2. Run the NI script that invokes Vivado to build a project and compile the intermediate design files: vivado -mode batch -source scriptsDFX/project_create_and_build.tcl
      • The *.tcl script is one of the files that the system creates by clicking Generate intermediate files. You must run this script from the base folder of the intermediate files.
      • This command builds a project and starts the compilation process. Depending on machine capability and project complexity, the process can take upwards of five hours.
      • After the execution of this command, the compilation outputs are added to the base folder in which you started the execution of the command.
  5. Copy the compile output to the development system where the LabVIEW FPGA Module is installed.
    Note Skip this step if you are using Vivado locally.
    You must move the resulting build files into the same folder that LabVIEW placed the intermediate files into (for example, C:\NIFPGA\compilations\).
  6. Run the VI that makes a lvbitx from the build files.
    The title of the VI is niFpgaGenerateLvbitx.vi. You can find the VI in the scriptsDFX folder, together with the design files.