Trigger Synchronization Overview

The Trigger Synchronization instrument design library facilitates synchronizing triggers across multiple devices.

You can configure triggers to assert on the exact same clock cycle on different devices. The original trigger to be synchronized is received by one device, known as the master device, and that device distributes the trigger to all the other devices that need to receive the synchronized trigger, known as slave devices. This instrument design library contains LabVIEW FPGA VIs.

Synchronized triggers have a variety of useful applications, especially when used with multirecord acquisition and waveform generation:

  • Determine when to acquire and record data into memory
  • Determine when to generate waveform data
  • Allow you to start acquiring record data or generating waveform data on multiple devices on the same clock cycle

Synchronizing Triggers

To synchronize triggers, the trigger synchronization logic must run in a synchronized clock domain.

  1. Lock the clocks on all devices to the same Reference Clock.

    When locked to the same Reference Clock, the clock skew among the different devices is constant.

  2. Use the Configuration instrument design library to lock the Sample Clock or Data Clock to a specified Reference Clock.

    When the trigger synchronization logic on PXIe-5644/5645 devices runs in the Sample Clock domain, or in the Data Clock domain on PXIe-5646 devices, lock the Sample Clock or Data Clock to PXI_CLK10 on the chassis or to an external 10 MHz Reference Clock supplied through REF IN.

Common Periodic Time Reference

The master device detects the original unsynchronized trigger and distributes that trigger to the slave devices; however, the propagation time for the trigger signal to reach each of the slave devices may vary. To compensate for the difference in propagation times, all devices use a slower rate signal that is phase-aligned to the synchronized clock domain and has minimal skew between devices.

All devices use this slower rate signal, known as the common periodic time reference (CPTR), to determine when to evaluate the distributed trigger. The CPTR period must be greater than the worst-case trigger propagation time. The CPTR asserts on all devices on the same clock cycle.

Note The CPTR runs at 10 MHz on PXIe-5644/5645 devices and at 5 MHz on PXIe-5646 devices.

Common Periodic Time Reference Diagram

The following timing diagram illustrates how trigger distribution from master device to slave devices occurs and how the synchronized trigger asserts on all devices on the same clock cycle.


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  1. The master device detects the original unsynchronized trigger.
  2. The master device starts distributing the trigger following the next assertion of the CPTR signal.
  3. The master device continues to distribute the trigger on the distribution line until the next assertion of the CPTR signal.

    The period of the CPTR signal should be large enough to account for the propagation of the distribution signal from the master device to the slave devices. The distribution signal from the master device arrives at all the slave devices before the second assertion of the CPTR and therefore all master and slave devices can assert the synchronized trigger following this assertion of the CPTR signal. Because the CPTR signal asserts on the same clock cycle on all the devices, the synchronized trigger asserts on all the devices on the same clock cycle.

Sampled Reference Clock

On the VSTs, you can generate the CPTR signal using the Sampled Reference Clock signal that is accessible through an I/O node.

The following table describes the clock domain of the Sample Reference Clock on either the PXIe-5644R/5645 or the PXIe-5646 devices.

Device Sampled Reference Clock Domain Description
PXIe-5644R/5645 Sample Clock The Sampled Reference Clock is a signal in the Sample Clock domain that asserts on all devices on the same Sample Clock cycle as long as the Sample Clocks on all the devices are locked to the same external Reference Clock.
PXIe-5646 Data Clock The Sampled Reference Clock is a signal in the Data Clock domain that asserts on all devices on the same Data Clock cycle as long as the Sample Clocks on all the devices are locked to the same Reference Clock and the Data Clocks have been properly synchronized on all devices.

Code Examples

The following figures illustrate how the code might look on the FPGA for the master device and slave device, respectively.

Figure 1. Master Device
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Figure 2. Slave Device
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Hardware Setup

For trigger synchronization to work properly, consider the following key hardware setup details:

  • Ensure that the Sample Clocks on all the devices are locked to in-phase Reference Clocks, using either PXI_CLK10 on the backplane or external Reference Clocks on the front panel connectors.
  • On PXIe-5646 devices, ensure that the Data Clocks are properly synchronized across all PXIe-5646 devices.
  • Ensure that the Trigger Synchronization instrument design VIs are used within the Sample Clock domain on PXIe-5644/5645 devices or within the Data Clock domain on PXIe-5646 devices.
  • Ensure that the master device and slave device are writing to and reading from the correct trigger distribution line, respectively. For example, if PXI_Trig0 is written by the master to distribute the trigger to the slave devices in the chassis, ensure that all the slave devices are reading from PXI_Trig0 for the trigger distribution signal.
  • If devices are present on multiple bus segments of the chassis, ensure that the direction of the PXI trigger lines is set correctly in MAX. The triggers should move away from the segment that contains the master device.

Refer to the context help of the Trigger Synchronization LabVIEW VIs for more detailed information about the library interface.

Refer to the documentation for the Simple VSA/VSG sample project or the VST Streaming sample project for more information about synchronizing the PXIe-5646 Data Clocks across all devices using the instrument design libraries.