Configuration Overview
- Updated2023-07-20
- 2 minute(s) read
Configuration Overview
The Configuration instrument design library provides functionality to configure hardware settings and to check if the hardware is operating correctly.
This instrument design library is divided into the following sections to configure the different hardware subsystems on the device.
| Section | Description |
|---|---|
| RF In Subsystem | Use the RF In section of the Configuration instrument design library to configure the RF input subsystem and to check if it is operating correctly. The RF input subsystem controls the gain and filtering applied to the input signal and the local oscillator (LO) frequency used to downconvert the input signal. This section includes host VIs and FPGA VIs. |
| RF Out Subsystem | Use the RF Out section of the Configuration instrument design library to configure the RF output subsystem and to check if it is operating correctly. The RF output subsystem controls the power level of the output signal, the filtering applied to the output signal, and the LO frequency used to upconvert the output signal. This section includes host VIs and FPGA VIs. |
| I/Q In Subsystem | Use the I/Q In section of the Configuration instrument design library to configure the I/Q input subsystem of the PXIe-5645 and to check its status. The I/Q input subsystem controls the gain and terminal configuration of the input signal. This section includes host VIs and FPGA VIs. |
| I/Q Out Subsystem | Use the I/Q Out section of the Configuration instrument design library to configure the I/Q output subsystem of the PXIe-5645 and to check its status. The I/Q output subsystem controls the power level and terminal configuration of the output signal. It can also apply an offset and a common-mode offset to the output signal. This section includes host VIs and FPGA VIs. |
| Basecard Subsystem | Use the Basecard section of the Configuration instrument design library to configure the clocking on the basecard subsystem and to check if it is operating correctly. The basecard subsystem controls the Reference Clock, Sample Clock, DACs, and ADCs. This section includes host VIs and FPGA VIs. |
| 5644R FPGA | This library provides FPGA registers to access all the hardware subsystems of the PXIe-5644. This section contains FPGA VIs. |
| 5645R FPGA | This library provides FPGA registers to access all the hardware subsystems of the PXIe-5645. This section contains FPGA VIs. |
| 5646R FPGA | This library provides FPGA registers to access all the hardware subsystems of the PXIe-5646. This section contains FPGA VIs. |
Related Information
- Configuring the Subsystems
To configure the different hardware subsystems of your device, complete the following steps.
- Register Bus Overview
Use the Register Bus instrument design library to send register read and write instructions from your application on the host to the FPGA.
- Embedded Configuration Block Overview
Use the Embedded Configuration Block (ECB) instrument design library to store multiple hardware configurations in onboard memory and recall them from the FPGA.