Configuring the Subsystems

Each subsystem must be initialized once after power up using the initialization host VIs from the Configuration instrument design library. The initialization VIs configure hardware registers that are not modified by the clock configuration and RF configuration VIs, regardless of their input parameters. After you successfully initialize the hardware, subsequent calls to the initialization VIs have no effect on the hardware configuration.

You must configure the Reference Clock and the Sample Clock before using the RF Configuration VIs. Use the Basecard Configure Clocks VI to select the Reference Clock and lock the Sample Clock to the selected Reference Clock. After the Sample Clock is locked to the Reference Clock, the Sample Clock PXIe-5644/5645) or the Data Clock (PXIe-5646) in the device FPGA is enabled. The Basecard Configure Clocks VI reads the current clock configuration from the device and has no effect on the hardware configuration if the clock is already configured correctly and the clock PLLs are locked.

The instrument design library provides high-level configuration VIs that simplify the configuration to a single VI call, and it also includes low-level configuration VIs that provide full control of the configuration steps. Both the high-level and low-level configuration VIs use calibration data to select calibrated configurations for the specified frequency or power level. Use the Read Calibration Data VIs to read calibration data stored in the device.

High-level configuration VIs expose all the properties that can be configured on a subsystem and write them to the hardware using the Register Bus. For most applications, the high-level configuration VIs provide all the necessary functionality.

Use the low-level VIs when you need to use the Embedded Configuration Block or when you need to optimize reconfiguration performance by filtering out unnecessary register writes. Low-level configuration consists of the following steps:

After configuring the RF or I/Q hardware, use the corresponding Wait Until Settled VI to allow the hardware to settle prior to generating or acquiring a signal. The Configuration instrument design library includes a corresponding Wait Until Settled VI for RF input, RF output, I/Q input, and I/Q output.

The 5644R, 5645R, and 5646R FPGA libraries each include a Registers VI that contains all the registers needed to configure the corresponding hardware. Depending on your device, connect the 5644R Registers VI, the 5645R Registers VI, or the 5646R Registers VI to the Register Bus to enable configuration of the device by the host VIs. The following table provides more information about the 5644R, 5645R, and 5646R Registers VIs.