Digital waveform generators and analyzers include three independent internal delay mechanisms:

  • Dynamic generation delay
  • Dynamic acquisition delay
  • Exported sample clock delay

Each mechanism can delay data and clock positions by up to one full sample clock period. For valid frequencies and ranges for delays check the device specifications document.

For NI 6547/6548 devices, channels are arranged into three different banks for multibank data delay.

Note NI 656x devices have special considerations for legal delayed data settings for Sample clock frequencies between 25 and 50 MHz.

The following table lists the resolution of the delay mechanisms for the frequencies that the digital waveform generator/analyzer internal sample clock can produce. For externally supplied frequencies above 25 MHz that are not listed in this table, the delay resolution is 1/256 of the sample clock period.

Operating Frequency* Resolution/Step Size†
200 MHz 20 ps‡
100 MHz 39 ps‡
66.7 MHz 59 ps‡
50 MHz 78 ps
40 MHz 98 ps
33.3 MHz 117 ps
28.6 MHz 137 ps
25 MHz 156 ps

*Not all operating frequencies may be applicable on your device.

†These values are not supported for NI 6544/6545/6547/6548 devices.

‡For NI 656x devices, refer to the device specifications document for more information about the supported step sizes.