NI signal generators offer a number of options for configuring the clocking of your device. Clocking is used to control the rate at which signals are generated. An internal voltage-controlled crystal oscillator (VCXO) behaves as a Sample clock timebase for the signal generator. This Sample clock timebase is either configured or replaced by using one of the following methods:

  • Internal Sample clock—The internal Sample clock timebase is used to determine clocking rates. In Arbitrary Waveform mode, you can control this timebase by choosing a clock mode for your signal generator (Divide-Down or High-Resolution).
  • Reference clock—An external device is used as a Reference clock in the phase-locked loop (PLL) of the signal generator. This causes the Reference clock to phase-lock to the Sample clock timebase so that the frequency stability and accuracy of the Sample clock timebase matches that of the Reference clock.
  • External Sample clock—An external Sample clock directly drives the clocking of the signal generator.
Note   Refer to the Features Supported topic for your device to determine which clocking options are available on your signal generator.

Clock Mode

The clock mode is applicable only when using an internal Sample clock. The clock mode determines the method of deriving the Sample clock from the Sample clock timebase—the main timing component of the device. You can set the clock mode with the Clock Mode property or the NIFGEN_ATTR_CLOCK_MODE attribute.

There are three options for deriving the clock mode on the NI 5412/5421/5422/5441/5442: Divide-Down (Divide by N) Sampling, High-Resolution Sampling, and Automatic mode (the default mode for NI-FGEN).

Divide-Down Clocking Mode

Divide-Down clocking configures the Sample clock timebase. The Sample clock timebase is usually a voltage–controlled crystal oscillator (VCXO). The valid sample rates for Divide-Down clocking are integer divisions of the Sample clock timebase frequency. The sample rate is given by the formula:

SR = SCTF/n

where

SR = sample rate

n = integer from 1 to a maximum value for the specific device

SCTF = Sample clock timebase frequency for the specific device

For example, a signal generator with a Sample clock timebase frequency of 100 MS/s has available sample rates that are integer divisions of 100 MS/s, as shown in the following examples:

SCTF/1 = 100 MS/s

SCTF/2 = 50 MS/s

SCTF/3 = 33.333 MS/s

As the integer n increases, the available sample rate decreases. If you choose a sample rate other than an integer division of the Sample clock timebase, the device usually coerces the sample rate setting to the nearest sample rate or integer division of the Sample clock timebase.

Divide-Down clocking provides the lowest jitter Sample clock, and it is also referred to as /N or divide by n clocking.

High-Resolution Clocking Mode

High-Resolution clocking allows you to set the Sample clock frequency to any value from zero to the device Sample clock timebase frequency with a very fine resolution typically in the millihertz or microhertz range. This mode is useful for applications that require a precise clock source, which is not possible using the Divide-Down clocking scheme.

Automatic Clocking Mode

In Automatic clocking mode, NI-FGEN switches between Divide-Down and the High-Resolution clocking modes depending on the sample rate configured with the Sample Rate property or the NIFGEN_ATTR_ARB_SAMPLE_RATE attribute.