Delays (or phase shifts) the Sample clock, which delays the output of the module. Adjustment time can be positive or negative, but it must be less than or equal to the Sample clock period. The delay takes effect immediately after this VI is called.

To delay an external Sample clock, set the Sample Clock Absolute Delay property. Delaying the Sample clock can be useful when lining up the output of multiple modules or when intentionally phase shifting the output relative to a fixed reference such as the PLL Reference clock.

Note Calling this VI after calling the NI-TClk Synchronize VI breaks synchronization.


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Inputs/Outputs

  • civrn.png Instrument Handle —

    Instrument Handle identifies a particular instrument session.

    Instrument Handle is obtained from the niFgen Initialize VI, niFgen Initialize With Options VI, or the niFgen Initialize With Channels VI.

  • cdbl.png Adjustment Time —

    Adjustment Time specifies the amount of time to adjust the Sample clock delay.

    Units: Seconds (s)

  • cerrcodeclst.png error in (no error) —

    error in describes error conditions that occur before this node runs. This input provides standard error in functionality.

    Default value: no error

  • iivrn.png Instrument Handle Out —

    Instrument Handle Out passes a reference to your instrument session to the next VI.

  • ierrcodeclst.png error out —

    error out contains error information. This output provides standard error out functionality.