Calculates the mean, variance, and/or standard deviation of an input signal. This Express VI analyzes discrete frames of data rather than analyzing data continuously. This Express VI waits for N cycles to collect a frame of data before returning one valid output, where N is the number of samples in each frame. It then waits for another N cycles to return another valid output.


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Dialog Box Options

Option Description
Number of Samples Specifies the number of samples in each frame on which this Express VI performs statistical measurements.
Statistics Contains the following options:
  • Mean—Specifies whether to calculate and return the mean value of the input signal.
  • Standard deviation—Specifies whether to calculate and return the standard deviation of the current input signal.
  • Variance—Specifies whether to calculate and return the variance of the current input signal.
Execution Mode Contains the following options:
  • Outside single-cycle Timed Loop—Configures this Express VI to execute outside a single-cycle Timed Loop.

    If you select this option and place this Express VI inside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

  • Inside single-cycle Timed Loop—Configures this Express VI to execute inside a single-cycle Timed Loop.

    If you select this option and place this Express VI outside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

  • Latency—Displays the number of cycles between the last point in the input frame and the valid output, which is a single point. Latency is available only when you select Inside single-cycle Timed Loop.

Inputs/Outputs

  • cunkn.png input data —

    Specifies the input signal to measure.

    input data is a fixed-point number or integer with a maximum word length of either 32 bits if signed or 31 bits if unsigned.

  • input valid —

    Specifies whether the next data point has arrived for processing. Wire output valid of an upstream node to input valid to transfer data from the upstream node to this Express VI.

    To display this handshaking terminal, select Inside single-cycle Timed Loop in the configuration dialog box.

  • ready for output —

    Specifies whether downstream nodes are ready for this Express VI to return a new value. The default is TRUE. Use a Feedback Node to wire ready for input of a downstream node to ready for output of the current node.

    Note If ready for output is FALSE during a given cycle, output valid returns FALSE during that cycle.

    To display ready for output, select Inside single-cycle Timed Loop in the configuration dialog box.

  • cbool.png reset —

    Clears all internal states when this signal is TRUE.

    Outside the single-cycle Timed Loop, this Express VI clears all internal states on the same call that reset is TRUE. Inside the single-cycle Timed Loop, this Express VI clears all internal states on the first cycle that reset is FALSE after reset is TRUE.

  • iunkn.png mean —

    Returns the mean value of the input signal.

  • standard deviation —

    Returns the standard deviation of the input signal.

  • variance —

    Returns the variance of the input signal.

  • ibool.png output valid —

    Returns TRUE if this Express VI has computed a result that downstream nodes can use. After returning TRUE for the previous output frame, output valid returns FALSE and waits for the next frame to complete. Wire output valid to input valid of a downstream node to transfer data from this Express VI to a downstream node. To display output valid, select the Inside single-cycle Timed Loop option in the configuration dialog box.

  • ready for input —

    Returns TRUE if this Express VI is ready to accept new input data. Use a Feedback Node to wire ready for input to ready for output of an upstream node.

    Note If ready for input returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this Express VI during the following cycle. LabVIEW discards this data even if input valid is TRUE during the following cycle.

    To display ready for input, select Inside single-cycle Timed Loop in the configuration dialog box.