Calculates the DC (mean) and/or RMS values of an input signal. You also can use this Express VI to calculate the intermediate sum, mean square, or square sum values in order to save FPGA resources. This Express VI accepts frames of data, performs measurement on the input data, and returns a valid single result for each frame.


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Dialog Box Options

Parameter Description
Measurement Time Setup

Contains the following options:

  • Measurement time (s)—Specifies the measurement time (averaging time) in seconds for the Measurements you select. This Express VI always coerces the Measurement time (s) so it corresponds to an integer Actual number of measurement samples.
  • Actual number of measurement samples—Specifies the number of samples used to calculate the Measurements you select.If you want to save resources on the FPGA, enter a value that is a power of two for the Actual number of measurement samples.
  • Expected sample rate (S/s)— Specifies the sample rate of the input signal.
    Caution The actual sample rate is specified elsewhere in the FPGA application. If the sample rate changes, you must change the Expected sample rate in this Express VI. Otherwise, this Express VI might not behave as expected.
Windowing

Contains the following options:

  • Apply Hanning window—Specifies whether to apply a Hanning window to the input signal before calculating the measurement results. Selecting this option can reduce spectral leakage and achieve more accurate and stable results if the input signal contains periodic components. If you select this option, you cannot select the Square Sum measurement.
Execution Mode

Contains the following options:

  • Outside single-cycle Timed Loop—Configures this Express VI to execute outside a single-cycle Timed Loop.

    If you select this option and place this Express VI inside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

  • Inside single-cycle Timed Loop—Configures this Express VI to execute inside a single-cycle Timed Loop.

    If you select this option and place this Express VI outside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

  • Latency—Displays the number of cycles between the last point in the input frame and the valid output, which is a single point. Latency is available only when you select Inside single-cycle Timed Loop.
Measurements

Contains the following options:

  • DC (Mean)—Specifies whether to return the DC value of the input signal.
  • Sum—Specifies whether to return the sum of the input signals.
  • RMS—Specifies whether to return the RMS (Root Mean Square) value of the input signal.
  • Mean Square—Specifies whether to return the mean value of the squares of the input signals.
  • Square Sum—Specifies whether to return the sum of the squares of the input samples. You cannot select this option if you place a checkmark in the Apply Hanning window checkbox.

Inputs/Outputs

  • cunkn.png input data —

    Specifies the input signal to measure. input data is a fixed-point number or integer with a maximum word length of either 32 bits if signed or 31 bits if unsigned.

  • cbool.png reset —

    Clears all internal states when this signal is TRUE. Outside the single-cycle Timed Loop, this Express VI clears all internal states on the same call that reset is TRUE. Inside the single-cycle Timed Loop, this Express VI clears all internal states on the first cycle that reset is FALSE after reset is TRUE.

  • input valid —

    Specifies whether the next data point has arrived for processing. Wire output valid of an upstream node to input valid to transfer data from the upstream node to this Express VI.

    To display this handshaking terminal, select Inside single-cycle Timed Loop in the configuration dialog box.

  • ready for output —

    Specifies whether downstream nodes are ready for this Express VI to return a new value. The default is TRUE. Use a Feedback Node to wire ready for input of a downstream node to ready for output of the current node.

    Note If ready for output is FALSE during a given cycle, output valid returns FALSE during that cycle.

    To display ready for output, select Inside single-cycle Timed Loop in the configuration dialog box.

  • iunkn.png DC —

    Returns the DC value of the input signal.

  • sum —

    Returns the sum of the input signals.

  • square sum —

    Returns the sum of the squares of the input signals.

  • RMS —

    Returns the root mean square value of the input signal.

  • mean square —

    Returns the mean value of the squares of the input signals.

  • ibool.png output valid —

    Returns TRUE if this Express VI has computed a result that downstream nodes can use. After returning TRUE for the previous output frame, output valid returns FALSE and waits for the next frame to complete. Wire output valid to input valid of a downstream node to transfer data from this Express VI to a downstream node. To display output valid, select the Inside single-cycle Timed Loop option in the configuration dialog box.

  • ready for input —

    Returns TRUE if this Express VI is ready to accept new input data. Use a Feedback Node to wire ready for input to ready for output of an upstream node.

    Note If ready for input returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this Express VI during the following cycle. LabVIEW discards this data even if input valid is TRUE during the following cycle.

    To display ready for input, select Inside single-cycle Timed Loop in the configuration dialog box.

    • Refer to the support document at ni.com for more information about the accuracy of the DC and RMS Measurements VI.

    DC and RMS measurements contain common error sources.

    Conserving FPGA Resources

    The DC and RMS Express VI can calculate the DC and RMS values of an input signal. However, some of the operations for the calculation require significant FPGA resources. You can save FPGA resources by splitting the operations into two groups that run on the FPGA VI and the host VI, respectively. In the following calculations, you can perform the operations in blue on the host.

    DC = Sum/Actual number of measurement samples

    RMS = sqrt(Mean square)

    RMS = sqrt(Square Sum/Actual number of measurement samples)

    You also can save FPGA resources if Actual number of measurement samples is a power of two.

    Examples

    Refer to the following example files included with LabVIEW FPGA Module.

    • labview\examples\CompactRIO\FPGA Fundamentals\FPGA Math and Analysis\DC and RMS Measurement\DC and RMS Measurement.lvproj
    • labview\examples\R Series\FPGA Fundamentals\FPGA Math and Analysis\DC and RMS Measurement\DC and RMS Measurement.lvproj