Converts frequency, phase, and duty cycle parameters into fixed-point units normalized to the clock rate. Use the Normalize Signal Generation Parameters VI in a host VI to convert values for the following FPGA VIs: Sine Wave Generator and Square Wave Generator.


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Inputs/Outputs

  • cdbl.png FPGA clock rate (Hz) —

    FPGA clock rate (Hz) specifies the clock rate at which the compilation tools compile the FPGA VI.

  • cdbl.png frequency (Hz) —

    frequency (Hz) specifies the frequency of the generated signal in hertz.

  • cdbl.png phase offset (deg) —

    phase offset (deg) specifies the phase in degrees.

  • cdbl.png duty cycle (%) —

    duty cycle (%) specifies the percentage of time the square wave remains high over one period.

  • cerrcodeclst.png error in (no error) —

    error in describes error conditions that occur before this node runs. This input provides standard error in functionality.

  • iunkn.png frequency (periods/tick) —

    frequency (periods/tick) returns the scaled frequency, in number of periods per clock cycle, of the FPGA clock. This value is an unsigned fixed-point data type with a 32-bit word length and a 0-bit integer word length.

  • iunkn.png phase offset (periods) —

    phase offset (periods) returns the scaled phase offset in number of periods. This value is an unsigned fixed-point data type with a 32-bit word length and a 0-bit integer word length.

  • iunkn.png duty cycle (periods) —

    duty cycle (periods) returns the scaled duty cycle in number of periods. This value is an unsigned fixed-point data type with a 32-bit word length and a 0-bit integer word length.

  • ierrcodeclst.png error out —

    error out passes error or warning information out of a VI to be used by other VIs. Right-click the error out indicator on the front panel and select Explain Error or Explain Warning from the shortcut menu for more information about the error.

  • idbl.png actual frequency (Hz) —

  • idbl.png actual phase offset (deg) —