Converts the desired sample rate to the appropriate count for the Loop Timer Express VI and computes the achievable sample rate for use with other Scaling VIs.


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Inputs/Outputs

  • cdbl.png FPGA clock rate (Hz) —

    FPGA clock rate (Hz) specifies the clock rate at which the compilation tools compile the FPGA VI.

  • cdbl.png sample rate (S/s) —

    sample rate (S/s) specifies the sampling rate for the signal in samples per second.

  • cerrcodeclst.png error in (no error) —

    error in describes error conditions that occur before this node runs. This input provides standard error in functionality.

  • iu32.png count (ms/S) —

    count (ms/S) returns the time between loop iterations in milliseconds.

  • idbl.png actual sample rate (S/s) —

    actual sample rate (S/s) returns the achievable sampling rate based on FPGA clock rate (Hz).

  • ierrcodeclst.png error out —

    error out contains error information. This output provides standard error out functionality.