In an FPGA VI, double-click the Input Node of a Timed Loop or right-click the node and select Configure Input Node from the shortcut menu to display this dialog box.

Use this dialog box to configure options on a single-cycle Timed Loop in an FPGA VI.

Note To specify the clock that controls a single-cycle Timed Loop, you also can use the Source Name input on the Input Node of the Timed Loop. By using an FPGA clock control configured as an input terminal on the connector pane, you can create subVIs with configurable clocks.

You can specify that a single-cycle Timed Loop uses any clock under the FPGA target in the Project Explorer window. You can have multiple single-cycle Timed Loops on a block diagram, each executing at different clock rates. Double-click the Input Node of a Timed Loop to display this dialog box.

This dialog box includes the following components:

Option Description
Loop Name Specifies the name of the single-cycle Timed Loop in the FPGA VI. You can use this name to identify the single-cycle Timed Loop in the Timing Violation Analysis window.
Require removal of implicit enable signals Requires the compiler to remove the implicit enable signal from the single-cycle Timed Loop. When it is not possible for the compiler to remove the implicit enable signal, the compiler returns a code generation error. By default, this checkbox does not contain a checkmark.
Note This option is only visible for targets that support the removal of implicit enable signals. Refer to your target hardware documentation for more information about support for removing implicit enable signals.
Use Parent Diagram Specifies that the single-cycle Timed Loop uses the top-level FPGA target clock.
Select Timing Source Allows you to select a clock other than the top-level FPGA target clock. You can select the FPGA target base clock or any FPGA target clock you derive.
Available Timing Sources Displays a list of the available timing sources that appear under the FPGA target in the Project Explorer window.
Selection Displays details about the clock you select as the single-cycle Timed Loop clock.