You can display this page in the following two ways:

  • If an FPGA build specification does not exist, right-click Build Specifications under an FPGA target in the Project Explorer window and select New»Compilation to display the Compilation Properties dialog box. Select Xilinx Options from the Category list to display this page.
  • If an FPGA build specification exists, right-click the build specification and select Properties from the shortcut menu to display the Compilation Properties dialog box. Select Xilinx Options from the Category list to display this page.
Note Not all FPGA targets support the Xilinx Options page. If the target does not support this page, it does not appear in the Category list. Additionally, depending on your target, you may see the Xilinx Options Page for Vivado (Compilation Properties Dialog Box).

Use this page to define the Xilinx ISE options to use when you compile an FPGA VI. The options you can specify depend on your specific FPGA target. Refer to the support document at ni.com for more information about NI hardware supported by each Xilinx compilation tool.

In general, you do not need to adjust the options on this page unless the FPGA VI fails to compile. Use the information from the Compilation Status window to determine which options on this page might help the FPGA VI compile successfully. Refer to the Xilinx website at www.xilinx.com for information about different design strategies and optimization options.

This page contains the following components:

Option Description
Use recommended settings Specifies that the Xilinx compiler uses the options that the target provides. By default, this checkbox contains a checkmark. Remove the checkmark to customize Xilinx options on this page.
Design Strategy Specifies a set of Xilinx options for the application. You can select from preset configurations to minimize the compilation time, maximize timing performance, or optimize the design area. You can override any of the options of a design strategy to create a custom configuration.
  • Balanced—Selects options that balance the compilation time with the amount of effort the Xilinx compiler uses to meet the timing and design objectives of the FPGA application.
  • Minimum Compilation Time—Selects options that minimize the compilation time by reducing the mapping effort of the Xilinx compiler.
  • Timing Performance—Selects options that maximize the timing performance of the FPGA application.
  • Area—Selects options that optimize the area usage on the FPGA.
  • Custom—Indicates that options might not match any of the preset configurations.
Synthesis Optimization Goal Specifies the synthesis optimization goal of the Xilinx compiler. Synthesis is the component of the Xilinx compilation process that creates logic gates from the design of the FPGA VI.
  • Speed—Configures the Xilinx compiler to reduce the logic levels in the design implementation.
  • Area—Configures the Xilinx compiler to minimize the total amount of logic in the design implementation.
Synthesis Optimization Effort Level Specifies the effort level the Xilinx compiler uses during synthesis. The effort levels are relative to each other and not absolute levels.
  • Normal—Configures the Xilinx compiler to optimize the design using minimization and algebraic factoring algorithms.
  • High—Configures the Xilinx compiler to perform additional optimizations for the specific FPGA architecture. Specifying the High synthesis optimization effort level increases the compilation time because the Xilinx compiler attempts multiple optimization algorithms to determine the best result for the target architecture.
Map Overall Effort Level Specifies the effort level the Xilinx compiler uses to map the FPGA VI to the FPGA. The effort levels are relative to each other and not absolute levels.
  • Default Xilinx setting—Configures the Xilinx compiler to use the Xilinx default effort level for mapping.
  • Standard—Configures the Xilinx compiler to use the standard level of effort.
  • High—Configures the Xilinx compiler to use the highest level of effort when compiling the FPGA VI. The High effort level takes more time to compile than other effort levels.
Place and Route Overall Effort Level Specifies the effort level of the Xilinx compiler uses to place the logic blocks and route the combinatorial paths on the FPGA. The effort levels are relative to each other and not absolute levels.
  • Standard—Configures the Xilinx compiler to use the standard level of effort.
  • High—Configures the Xilinx compiler to use the highest level of effort when compiling the FPGA VI. The High effort level takes more time to compile than other effort levels.
Use random value for starting placer cost table Specifies a random value for the Starting Placer Cost Table property of the Place and Route process in the Xilinx tools. Enabling this checkbox will not initiate code generation, but could impact performance and device utilization results. Refer to the Xilinx website at www.xilinx.com for more information about place and route properties.