The IP Integration Node can return the following error codes. Refer to the KnowledgeBase for more information about correcting errors in LabVIEW.

Code Description
−61146 IP Integration Node must have a clock enable port. IP Integration Node does not have an IP Enable Signal selected but is placed inside a Case structure. If you place an IP Integration Node inside a Case structure, you must specify a clock enable signal for the IP. To specify this signal, right-click the node, select Configure>>Clock and Enable Signals from the shortcut menu, and select the appropriate IP port(s) from the list of possible IP Enable Signal(s). If the IP does not have a port that maps to a clock enable signal, either move the IP Integration Node outside the Case structure or add such a port and specify it using the method described above.
−61098 Derived clock required. You must wire a derived clock to the derived clock input of this IP Integration Node.
−61087 Files changed requiring node reconfiguration. The following files have changed since the IP Integration Node was configured: <ChangedFiles> You must reconfigure the node to ensure the simulation model is up to date and the interface has not changed.
−61086 File(s) do not exist. The following file(s) referenced by the IP Integration Node do not exist on disk: <MissingFiles> Reconfigure the IP Integration Node so it does not depend on these files or add the files on disk in a location the IP Integration Node expects.
−61085 IP not supported on current target. The IP Integration Node is not configured to support the <FpgaDeviceFamily> FPGA device family used on the current FPGA target.
−61084 Relative clock rate mismatch. The configured Relative clock rate of <ConfiguredRelativeClockRate> does not match the actual relative rate of <ActualRelativeClockRate> between the single-cycle Timed Loop clock and the clock specified as the Derived Multiple of Timed Loop Clock in the configuration of the IP Integration Node. Update the configured Relative clock rate or use a different derived clock.
−61068 Unrelated over clock error. The clock wired to the overclock input is not related to the single-cycle Timed Loop clock on which the IP Integration Node or the Xilinx IP Integration Node runs. Select a clock that is related to the single-cycle Timed Loop clock.