The FPGA Module can return the following general error codes. Refer to the KnowledgeBase for more information about correcting errors in LabVIEW.

Code Description
−61501 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: The XDC constraints file is missing a required macro (e.g. <macro_ClipConstraints>).
−61500 An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information: LabVIEW could not read a CLIP XML file.
−61499 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
−61498 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: Required tag was not found in the resource file.
−61497 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: An unsupported register offset was requested.
−61496 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: An unexpected case was reached.
−61495 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: A path tag specified a value that is not a path.
−61494 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: An IP Generator VI did not match the required interface.
−61493 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: The specified IP Generator VI could not be found.
−61492 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: Error accessing FPGA provider.
−61491 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: An IP Generator is missing the required VI Path Tag.
−61488 An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support with following information: A required XML tag was not found.
−61445 The handshake is outside a single-cycle Timed Loop. Handshake items are supported only inside a single-cycle Timed Loop.
−61405 The operation failed because you do not have a physical target specified for this FPGA target. Right-click the FPGA target in the Project Explorer window, select Properties, and enter an FPGA target resource name in the Resource text box.
−61404 LabVIEW encountered a target-specific error or warning.
−61403 LabVIEW is unable to interact with the current target because a required file is missing or inaccessible. Check that the FPGA target-specific driver software is installed correctly.
−61402 LabVIEW lost communication with the device. The resource for the target was disconnected or removed. If the target is located remotely, the remote system might be turned off or there might be a network problem.
−61400 Operation failed because the type of the hardware specified in the project and/or in the VI does not match the type of the hardware that was physically accessed.
−61399 Execution of the FPGA VI on the development computer is not supported for the given item/node in the custom VI used for FPGA I/O.
−61398 FPGA VI simulation failed because either the path for the specified custom VI for FPGA I/O simulation is missing or incorrect, or the specified custom VI for FPGA I/O simulation uses an incorrect connector pane. Check the custom VI path on the Simulation page of the target settings or check that the VI matches the required interface.
−61397 Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O does not conform to the calling requirements of the FPGA VI.
−61396 Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O called a VI or a function that returned an error.
−61395 Execution of the FPGA VI on the development computer failed because the custom VI for FPGA I/O is not executable.
−61394 This VI is supported only when the Execution Stage is Running.
−61239 FIFO execution is only supported under FPGA targets.
−61238 Memory execution is only supported under FPGA targets.
−61235 The value wired into the FIFO In input of a FIFO Method Node corresponds to a FIFO item that does not match the configuration of the FIFO Method Node.
−61234 The value wired into the FIFO In input of a FIFO Method Node does not correspond to any FIFO item in the project nor to any VI-defined FIFO.
−61233 The value wired into the FIFO In input of a FIFO Method Node is an empty string. Make sure the wired value corresponds to a FIFO item in the project or to a VI-defined FIFO .
−61232 The value wired into the Memory In input of a Memory Method Node corresponds to a memory item that does not match the configuration of the Memory Method Node.
−61231 The value wired into the Memory In input of a Memory Method Node does not correspond to a memory item in the project or to any VI-defined memory.
−61230 The value wired into the Memory In input of a Memory Method Node is an empty string. Make sure the wired value corresponds to a memory item in the project or a VI-defined memory.
−61229 The value wired into the Register In input of a Register Method Node corresponds to a Register item that does not match the configuration of the Register Method Node.
−61228 The value wired into the Register In input of a Register Method Node does not correspond to a Register item in the project or to any VI-defined Register.
−61227 The value wired into the Register In input of a Register Method Node is an empty string. Make sure the wired value corresponds to a Register item in the project or to a VI-defined Register.
−61226 The value wired into the Handshake In input of a Handshake Method Node corresponds to a Handshake item that does not match the configuration of the Handshake Method Node.
−61225 The value wired into the Handshake In input of a Handshake Method Node does not correspond to a Handshake item in the project or to a VI-defined Handshake.
−61224 The value wired into the Handshake In input of a Handshake Method Node is an empty string. Make sure the wired value corresponds to a Handshake item in the project or to a VI-defined Handshake.
−61223 Register execution is only supported under FPGA targets.
−61222 Handshake execution is only supported under FPGA targets.
−61207 Internal error: DiagramReset did not clear within the timeout period. Please contact National Instruments Technical Support at ni.com/support.
−61199 Execution has terminated because an I/O item that does not support execution on the development computer with real I/O has been encountered. You can execute an FPGA VI on the development computer with real I/O only when all of the I/O items you use in the FPGA VI support this mode of execution.
−61166 HDL Interface Node file conflict. The file at <FilePath> conflicts with another file of that name that has already been created. Reconfigure the HDL Interface Node to point to the correct copy of the file or rename this file.
−61083 A hardware clocking error occurred. A derived clock lost lock with its base clock during the execution of the FPGA VI. If any base clocks with derived clocks are referencing an external source, make sure that the external source is connected and within the supported frequency, jitter, accuracy, duty cycle, and voltage specifications. Also verify that the characteristics of the base clock match the configuration specified in the FPGA Base Clock Properties dialog box. If all base clocks with derived clocks are generated from free-running, on-board sources, please contact National Instruments technical support at ni.com/support.
−61082 The current target does not have sufficient DMA control line sets available. Too many sets of DMA control lines have been requested or some requests are conflicting. The current target has <NUM_CONTROL_SETS> sets of DMA control lines. Review the list of requestors and remove one or more requestors to free up resources.
−61081 Insufficient DMA channels available on the current target. Too many DMA channels have been requested or some requests are conflicting. The current target has <NUM_CHANNELS> DMA channels. Review the list of requested channels and remove one or more requestors to free resources.
−61080 This target does not support FPGA interrupts. Remove the Interrupt node from your FPGA VI or use a target that supports FPGA interrupts.
−61079 Insufficient address space on the FPGA for certain registers. The following components are present in the project: <IPNames>. The registers for each component require <RegisterBlockSizes> bytes of address space respectively. Total available address space on the FPGA for these registers is <AvailableAddressSpace> bytes. To free address space on the FPGA, remove some of the components listed above from the project and/or remove some of the controls and indicators from the top-level FPGA VI.
−61070 The compiled bitfile for the specified VI contains information that is no longer valid or is corrupt. Recompile the VI to correct this error.
−61069 This bitfile was created in a more recent version of LabVIEW and is incompatible with this version.
−61061 Nested libraries are currently not supported in FPGA VIs.
−61048 This target does not support DMA output from the host to the target.
−61046 An error was detected in the communication between the host computer and the FPGA target. If you are using any external clocks, make sure they are connected and within the supported specifications. Also, verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support.
−61045 Usage of locals is restricted on synchronous controls/indicators. You cannot use a <readwrite> local on the <ctrlind> <Name>. Disable the Synchronous display option on the front panel object to solve the problem.
−61044 The target does not have enough address space to accommodate the number of registers requested. The top-level FPGA VI front panel window contains too many controls and indicators. Group front panel objects into clusters to reduce the number of addresses needed to meet the communication needs of the application.
−61043 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: These required tags in <Path>\resource.xml file are missing:- <HardwareInterface> <Type> - <MostSignificantAddressLine>
−61042 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: The address requested <Address> for <RegName> is outside of the allowable range specified in <Path>\resource.xml. Check the following tags: <MostSignificantAddressLine> and <LeastSignificantAddressLine>.
−61041 Register name conflict. The front panel object <RegisterName> is conflicting with another register. Change the name of the front panel object to solve the problem.
−61040 Unsupported access strategy. The selected access strategy is not supported by the selected communication interface.
−61024 The device type that has been configured in this function does not match the actual type of the device.
−61023 The device at the address that was configured in this function is no longer available.
−61022 The FPGA target does not support running the FPGA VI in simulation mode.
−61019 A digital I/O resource cannot be accessed in a single-cycle Timed Loop from both a Digital Output function and a Digital Port Output function.
−61018 An error occurred downloading the VI to the FPGA device. Verify that the target is connected and powered and that the resource of the target is properly configured.
−61014 The device does not exist or is not accepting any connections.

Possible Reasons:

- The resource for the target is not correct or the target resource specified does not exist.

-If the target is located remotely:

  • The remote system might be turned off.
  • The software to use the device on the remote system might not be properly installed.
  • You might not have networking properly configured to access the remote system.
  • You might not have permissions properly set for any servers used to access the target.
61004 Occurrence traceback failed. The code generator was unable to trace back the use of an occurrence to a single generate occurrence. Occurrence is not statically bound.
61005 Bad Clock Rate for operation. The Clock Rate is not supported for analog components.
61006 The alias used by this FPGA Device I/O function, I/O Method Node, or I/O Property Node does not exist.