FIFO Error Codes (FPGA Module)
- Updated2025-01-28
- 3 minute(s) read
FIFOs can return the following error codes. Refer to the KnowledgeBase for more information about correcting errors in LabVIEW.
| Code | Description |
|---|---|
| −61504 | Unsupported FIFO method. The Flush method is not supported on the current target. Specify another target if you want to use the Flush method, or you can specify another FIFO method. |
| −61413 | FIFO with handshaking interface is outside a single-cycle Timed Loop. FIFOs do not support the handshaking interface outside of single-cycle Timed Loops. Place the FIFO inside a single-cycle Timed Loop, or use the timeout interface. |
| −61412 | Missing feedback node after Ready For Input terminal. You must connect a feedback node after the Ready For Input terminal for FIFO Write methods that use the handshaking interface. |
| −61411 | FIFO invokes methods with incompatible interfaces. FIFOs cannot invoke Write/Read methods that use a combination of the handshaking interface and the timeout interface. Specify the same interface for all Write/Read methods invoked by this FIFO. |
| −61410 | Target does not support the handshaking interface on this FIFO. Your target does not support the handshaking interface on this type of FIFO. To use the handshaking interface, specify another type of FIFO. Tip: All targets support the handshaking interface on target-scoped FIFOs. |
| −61099 | Built-in FIFO used in external clock domain. A FIFO configured with built-in control logic is used in an external clock domain. You can use only slice fabric for FIFO control logic when the FIFO is in a clock domain that might be stopped during reset, including all external clock domains. In the FIFO Properties dialog box, change the control logic to slice fabric. |
| −61088 | Built-in FIFO not supported on current target. The current target does not support built-in control logic for FIFOs. In the FIFO Properties dialog box, change the Control Logic to Slice Fabric or Target Optimal. |
| −61066 | Incompatible clock domains between FIFO count method and FIFO write/read method. The Get Number of Elements to Write method must be in the same clock domain as the Write method. The Get Number of Elements to Read method must be in the same clock domain as the Read method. |
| −61053 | Insufficient DMA channels available. The application is requesting more DMA channels than the target hardware supports. These channels may be requested by different FPGA FIFO items in the project or by other components. |
| −61052 | FIFO missing a function. The <Scope> FIFO needs to have both a Read method and a Write method present on the block diagram. Add a <PortType> function on the block diagram for this FIFO. |
| −61051 | Multiple FIFOs using the same DMA channel. At least one DMA channel is used by several FIFOs, which is not supported. Configure FIFOs to use a unique DMA channel. |
| −61050 | Clock domain crossing is not supported for FIFO implementation. The <Scope> FIFO is configured to use an implementation of <MemoryType> but has read and write interfaces in different clock domains. If you want to read and write in different clock domains, select Block Memory from the Implementation pull-down menu in the FIFO Properties dialog box for the <Scope> FIFO . |
| −61020 | FIFO timeout not supported. The selected FIFO function attempts to block execution with a non-zero timeout. Objects inside the single-cycle Timed Loop cannot block execution. When using an FPGA FIFO function inside a single-cycle Timed Loop, wire a constant of zero to the Timeout input. Otherwise, replace the Timed Loop with a While Loop. |
| −61013 | The FIFO Method Node reached the timeout before being able to access the FIFO. This error is due to another FIFO Method Node accessing the same FIFO and not completing before the current method timed out. |
| −61012 | The FPGA VI reference used to initialize the FIFO is no longer valid. |
| −61010 | You are trying to read from, write to, or close a FIFO that has not been initialized by the InitFIFO method. |