The FPGA Module can return the following compilation error codes. Refer to the KnowledgeBase for more information about correcting errors in LabVIEW.

Code Description
−61490 An internal error has occurred. This is normally generated by a user request to cancel an operation. No user visible feedback is given for this error.
−61462 The design was unable to meet timing requirements due to a pulse width violation.
−61461 This version of LabVIEW does not support the requested FPGA compilation tools.
−61459 The selected target requires 64-bit Xilinx tools, but the system uses a 32-bit OS.
−61458 Target does not support terminals configured for variable and bounded size arrays. One or more terminals on this wire are configured to accept variable or bounded size arrays, which this target does not support. Place a checkmark in the "Autopreallocate arrays and strings" checkbox in the Execution section of the VI Properties dialog box.
−61457 The compilation status file is missing or corrupt.
−61456 The FPGA design did not meet timing requirements and the source of the timing failure could not be located automatically.
−61455 Some of the compilation steps were not executed.
−61454 Some signals were not properly constrained in the design.
−61453 The constraints file was not used in the compilation.
−61452 The compilation failed due to resource overmapping.
−61451 The compilation failed due to timing violations.
−61450 The compilation failed due to a Xilinx error.