Clocks can return the following error codes. Refer to the KnowledgeBase for more information about correcting errors in LabVIEW.

Code Description
Code Description
−61156 Clock domain crossing is not supported for Occurrences.
−61138 Invalid top-level clock for target. The currently configured top-level clock, <InvalidTopClockName>, is not supported as a top-level clock for this FPGA target.<TargetSpecificFilteringMessage>Select a supported top-level clock from the FPGA Target Properties dialog box or reconfigure the current top-level clock. Refer to the FPGA target documentation for more information about supported top-level clocks.
−61067 Clock resource limit exceeded. This application uses more clocking resources for derived clocks than are available on the target. <NumberOfMMCMsUsed> Mixed-Mode Clock Managers (MMCMs) are used, however only <NumberOfMMCMsAvailable> are available to generate derived clocks.Reduce the number of derived clocks used in your application.
−61060 Clock domain crossing is not selected for the memory item. The memory Read and Write interfaces are located in different clock domains and the Dual Clock Interface option is not selected. Either place both interfaces in the same clock domain or place a checkmark in the Dual Clock Interface checkbox in the Memory Properties dialog box.
−61039 Clock resource limit exceeded. This application uses more clock resources than are available on the target. <NumberOfBUFGsUsed> clock buffers (BUFGs) are used, however only <NumberOfBUFGsAvailable> are available.Reduce the number of clocks used in your application.
−61037 Clock requested for From-To constraint does not exist.
−61033 Two timing sources in this application have the same clock signal name.
−61032 The available hardware cannot generate a derived clock.
−61031 There are no configured clocks for this application. Please configure a clock in the project tree.
−61030 Clock resource limit exceeded. This application uses more global clock nets than are available on the target. <NumberOfNetsUsed> global clock nets are used however only <NumberOfNetsAvailable> are available.Reduce the number of clocks used in your application.
−61029 VHDL signal names for clocks must contain "Clk" or "Clock". The first letter can be upper or lower case, but subsequent letters must be lower case.
−61028 A plug-in developer for a LV FPGA target did not provide timing constraints for all top level clocks.
−61027 Clock resource limit exceeded. This application uses more clocking resources for derived clocks than are available on the target. <NumberOfDCMsUsed> Digital Clock Managers (DCMs) are used however only <NumberOfDCMsAvailable> are available to generate derived clocks.Reduce the number of derived clocks used in your application.
−61026 A clock name was found that is not configured.
61058 Invalid clock for single-cycle Timed Loop. The selected single-cycle Timed Loop is configured to use the clock <ActualClockName> as a timing source. This clock either does not exist in the project or is invalid.Select a valid clock by right-clicking the Input Node of the single-cycle Timed Loop and selecting Configure Input Node or create a valid clock in the Project Explorer window with the name <ActualClockName>.