In this part of the tutorial, you create the consumer loop that processes the data generated by the producer loop. The consumer loop uses a While Loop instead of a Timed Loop because processing the data is a lower priority task than generating the data. That is, if hardware resources become limited, it is more important to generate the data within a bound timeframe than it is to process it.

Creating the Consumer Loop

It is typical to synchronize the While Loop and the Timed Loop using a Wait Until Next ms Multiple function. Synchronizing the loops in this fashion is not necessary, but it provides the While Loop with the execution time that remains in a period after the Timed Loop finishes executing.

Complete the following steps to create a consumer loop with the same period as a producer loop:

1. Within the block diagram of Real-Time Main.vi, place a While Loop below the Timed Loop.
2. Place a Wait Until Next ms Multiple function within the While Loop.
3. Right-click the millisecond multiple input of the Wait Until Next ms Multiple function and select Create»Constant from the short-cut menu.
4. Enter 250 as the constant to match the period of the Timed Loop.

Transferring Data Deterministically from the Producer Loop to the Consumer Loop

LabVIEW provides many methods for transferring data, some of which are deterministic and some of which are not. RT FIFOs are an example of a deterministic data communication method. To achieve determinism, RT FIFOs preallocate memory for the data transfer before run time, thereby preventing unforeseen delays writing to memory. RT FIFOs buffer and transfer data in a first-in, first-out order. You can find the RT FIFO functions on the Functions palette under Real-Time»RT FIFO. Refer to the Data Communication Methods in LabVIEW help topic to learn about other data communication methods available to you.

Complete the following steps to transfer data from the producer loop to the consumer loop using RT FIFOs:

1. Place an RT FIFO Create function outside and to the left of the loops.
2. Replace the indicator in the Timed Loop with an RT FIFO Write function.
   Note   Make sure to wire the output of the Random Number function to the element input of the RT FIFO Write function.
3. Place an RT FIFO Read function inside the While Loop.
4. Place an RT FIFO Delete function outside and to the right of the loops.
5. Wire a DBL Numeric Constant to the type input of the RT FIFO Create function.
6. Wire the rt fifo output of the RT FIFO Create function to the rt fifo input of the other three RT FIFO functions.
7. Right-click the Loop Condition icon of the While Loop and select Create Control from the short-cut menu to create a Stop button.
8. Place a Case structure within the While Loop.
9. Select False in the Case structure selector label.
10. Wire the empty? output of the RT FIFO Read function to the case selector of the Case structure.
11. Right-click the element out output of the RT FIFO Read function and select Create»Indicator from the short-cut menu.
12. Place the indicator inside the Case structure.
13. Wire the indicator to the element out output of the RT FIFO Read function.

Adding Error Handling

It is a best practice to wire the error terminals for functions. This allows you to pass error information through the VI and handle errors appropriately without suspending the execution of the VI.

Complete the following steps to wire errors in Real-Time Main.vi:

1. Resize the Input node of the Timed Loop to include five inputs.
2. Right-click the bottom input of the Timed Loop Input node and select Select Input»Error from the short-cut menu.
3. Wire the error out output of the RT FIFO Create function to the Error input of the Timed Loop Input node.
4. Wire the Error output of the Left Data node of the Timed Loop to the error in input of the RT FIFO Write function.
5. Wire the error out output of the RT FIFO Write function to the Error input of the Right Data node of the Timed Loop.
6. Place a Merge Errors function outside and to the right of the loops.
7. Wire the Error output of the Output node of the Timed Loop to the top input of the Merge Errors function.
8. Wire the error out output of the RT FIFO Create function to the error in input of the RT FIFO Read function.
9. Wire the error out output of the RT FIFO Read function through the Case structure and to the bottom error in input of the Merge Errors function.
10. Wire the error out output of the Merge Errors function to the error in input of the RT FIFO Delete function.
11. Right-click the error out output of the RT FIFO Delete function and select Create»Indicator.
12. Right-click one of the two While Loop error tunnels and select Replace with Shift Register from the short-cut menu.
13. Click the other While Loop error tunnel to replace it with a shift register.
14. Select True in the Case structure selector label.
15. Connect the error wire through the Case structure.
16. Save the VI.
17. In the Project Explorer window, right-click the VI and select Deploy from the short-cut menu.

Result

When you run Real-Time Main.vi, the producer loop assumes highest priority and writes values generated by the RT target to the RT FIFO buffer. The consumer loop reads the values from the RT FIFO buffer whenever the CPU is available during each period.