DRAM on an FPGA Target
- Updated2023-02-17
- 1 minute(s) read
DRAM on an FPGA Target
Dynamic RAM (DRAM) is a type of random access memory used to store and access larger sets of data than block RAM (BRAM) or look-up tables (LUTs). DRAM is not available on all FPGA targets.
Storing data in DRAM provides the following benefits:
- Additional space for large data sets that do not fit on the FPGA in BRAM or LUTs
- Lower latency access to memory than reading directly from the host
- Dedicated memory for data logging from embedded FPGAs that are not continuously connected to a host device
DRAM access has the following restrictions:
- Applications running on the FPGA cannot receive data from DRAM in a single clock cycle.
- Only one command can access DRAM memory at a time because DRAM requires sequential access.
- The sequential access required by DRAM prevents deterministic timing and may increase execution time.
Related Information
- Configurable Logic Blocks (CLBs) on an FPGA
A configurable logic block (CLB) is the basic repeating logic resource on an FPGA.
- Block RAM (BRAM) on an FPGA
Block RAM (BRAM) is a type of random access memory embedded throughout an FPGA for data storage.
- I/O Resources on an FPGA
Input and output (I/O) resources on an FPGA target are physical structures that allow you to connect an FPGA target to other devices in your system.
- Storing and Transferring Data
Store and transfer data on an FPGA using resource items like FIFOs, memory items, FPGA registers, or handshake items. You can also transfer data on an FPGA using panel controls or indicators.
- Introduction to FPGA Resources
Every FPGA has a set number of programmable logic, routing, I/O, and memory resources. The compiler uses these resources to implement code on the FPGA.