Configurable Logic Blocks (CLBs) on an FPGA
- Updated2023-02-17
- 1 minute(s) read
Configurable Logic Blocks (CLBs) on an FPGA
A configurable logic block (CLB) is the basic repeating logic resource on an FPGA. When linked together by routing resources, the components in CLBs execute complex logic functions, implement memory functions, and synchronize code on the FPGA.
CLBs contain smaller components, including flip-flops, look-up tables (LUTs), and multiplexers.
When you compile code to run on an FPGA target, LabVIEW implements much of the code using flip-flops, LUTs, and multiplexers.
Related Information
- Block RAM (BRAM) on an FPGA
Block RAM (BRAM) is a type of random access memory embedded throughout an FPGA for data storage.
- I/O Resources on an FPGA
Input and output (I/O) resources on an FPGA target are physical structures that allow you to connect an FPGA target to other devices in your system.
- DRAM on an FPGA Target
Dynamic RAM (DRAM) is a type of random access memory used to store and access larger sets of data than block RAM (BRAM) or look-up tables (LUTs).
- Storing and Transferring Data
Store and transfer data on an FPGA using resource items like FIFOs, memory items, FPGA registers, or handshake items. You can also transfer data on an FPGA using panel controls or indicators.
- Introduction to FPGA Resources
Every FPGA has a set number of programmable logic, routing, I/O, and memory resources. The compiler uses these resources to implement code on the FPGA.