Xilinx IP Data Storage

Implement IP related to FIFOs, RAMs, and ROMs.

Xilinx CORE Generator IP Nodes
Implement various Xilinx IP functions.
Block Memory Generator
Replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. Use this generator in all new Xilinx designs.
Distributed Memory Generator
Creates area and performance optimized ROM blocks, single and dual port distributed memories, and SRL16-based memories for Xilinx FPGAs.
FIFO Generator
Generates resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.
RAM-based Shift Register
Generates fast, compact FIFO-style registers, delay lines, or time-skew buffers up to 256 bits wide and up to 1024 words deep using Select RAM in SRL16 or SRLC32 mode.