The following table describes the differences between compiling a DSP48E or DSP48E1 function for an FPGA target and exporting the function for simulation:

Execution on an FPGA Target Simulation
Supported execution mode(s) Inside single-cycle Timed Loop
  • Inside single-cycle Timed Loop
  • Outside single-cycle Timed Loop
Wiring restrictions for optional terminals:
  • You can wire the acout output of one function only to the acin input of another function.
  • You can wire the bcout output of one function only to the bcin input of another function.
  • You can wire the pcout output of one function only to the pcin input of another function.
  • You can wire the multsignout output of one function only to the multsignin input of another function.
  • You can wire the carrycascout output of one function only to the carrycascin input of another function.
  • You cannot create branches for these wires, probe them, or create indicators for these output terminals.
 You can create branches for these wires, probe them, and create indicators for the output terminals.