Synthesis files contain the HDL code you want to integrate into an FPGA VI. Complete the following steps to add synthesis files to the IP Integration Node.

Note LabVIEW assumes the first file you add is the top-level file.
  1. Add the IP Integration Node to the block diagram.
  2. Double-click the node to configure it. The Name and Source page appears.
  3. Click the Add Synthesis File button:

    LabVIEW prompts you for a synthesis file to add.
  4. Choose the synthesis file to add and click the OK button. LabVIEW displays the synthesis file in the Synthesis File column of the IP Source table.
  5. (Optional) Set this file as the top-level file.
  6. Notice the Simulation Behavior column of this table. LabVIEW assigns a simulation behavior based on the type of file you added. You now have the following options:
    • Accept the simulation behavior LabVIEW assigned.
    • Change this simulation behavior.
    • Exclude the file from simulation.