After you add a synthesis file to the IP Integration Node, LabVIEW assigns a simulation behavior to that file. You can accept this behavior, change it, or exclude the file from simulation. The following table describes the available synthesis file types, the simulation behaviors LabVIEW automatically assigns to each type, and caveats when exporting certain types of files for simulation for Virtex-II FPGAs.

Note You must define a simulation behavior for each synthesis file even if you do not plan to export the FPGA VI for simulation.
Synthesis File Type Simulation Behavior that LabVIEW Assigns Notes Simulation Caveats for Virtex-II FPGAs
Netlist files User-defined LabVIEW uses a simulation model that you define. You must click the Set Simulation Behavior button to launch the Set Simulation Behavior dialog box. In this dialog box, use the Add File, Remove File, and Set as Top buttons to add .vhd files to the simulation model. You can obtain these files from the same source that provided the netlist file. Ensure that the netlist file name is the same as the netlist component name. The Generics and Support File Generation page of the IP Integration Node Properties wizard displays a Xilinx error and configuration of the IP Integration Node fails if these names differ. If the IP contains components that are specific to Virtex-II FPGAs, such as the BSCAN component, you cannot export the IP for simulation.
Xilinx IP configuration files Same as synthesis LabVIEW uses the .vhd simulation model generated by the Xilinx IP generator. You cannot export Xilinx IP configuration files for simulation with Virtex-II FPGAs.
.coe Same as synthesis N/A. N/A.
.vhd and other files Same as synthesis LabVIEW uses the .vhd synthesis file for simulation also.

.vhd files only: If the IP instantiates components for primitives that are specific to Virtex-II FPGAs, NI does not guarantee the accuracy of the simulation.