This memory interface provides an easy-to-use FIFO interface to external DRAM. The FIFO is exposed as separate read and write interfaces. Both the write-side and read-side data ports are 128-bit data words.

Signals for Writing to the FIFO

The following table lists the write-side I/O provided by the FIFO - 128 Bit memory interface.

Memory Interface I/O Data Type To Memory/From Memory Description
Full Bool From memory This signal is TRUE when data cannot be written into the FIFO.
Write_Data_Upper U64 To memory The upper 64 bits of the data to write into the FIFO.
Write_Data_Lower U64 To memory The lower 64 bits of the data to write into the FIFO.
Write Bool To memory Set signal to TRUE to place data from the Write_Data_Upper and Write_Data_Lower into the FIFO. Do not set Write to TRUE when Full is TRUE, as this leads to undefined behavior.

Signals for Reading from the FIFO

The following table lists the read-side I/O provided by the FIFO - 128 Bit memory interface.

Memory Interface I/O Data Type To Memory/From Memory Description
Data_Available Bool From memory This signal is TRUE when the values in Read_Data_Upper and Read_Data_Lower are valid and may be read.
Read_Data_Upper U64 From memory The upper 64 bits of the data to read from the FIFO. Read_Data_Upper is valid only when Data_Available is TRUE.
Read_Data_Lower U64 From memory The lower 64 bits of the data to read from the FIFO. Read_Data_Lower is valid only when Data_Available is TRUE.
Read Bool To memory Set this signal to TRUE to read data from Read_Data_Upper and Read_Data_Lower out of the FIFO. Do not set Read to TRUE when Data_Available is FALSE, as this leads to undefined behavior.

The write-side interface Full signal is TRUE when data cannot be added into the FIFO. If the Full signal is low, you can write into the FIFO by driving the Write_Data_Upper and Write_Data_Lower signals with your data and setting the Write signal to TRUE. Do not set the Write signal to TRUE when Full is TRUE, as this will lead to undefined behavior.

When read-side data on the Read_Data_Upper and Read_Data_Lower lines is available to be read, the Data_Available signal will be TRUE. After this data is read, set the Read signal to TRUE. Do not set the Read signal to TRUE when Data_Available is FALSE, as this will lead to undefined behavior.

The FIFO - 128 Bit memory interface requires that you define the clock domains of the single-cycle timed loop from which the read-side and write-side interfaces are accessed. Configure these interfaces by way of the Clock Selections property page for the corresponding DRAM bank item in the LabVIEW project. Configure the Write_Clock signal to be driven with the LabVIEW FPGA clock resource that you are using to clock the single-cycle timed loop that is accessing write-side interface. Likewise, configure the Read_Clock signal to be driven with the LabVIEW FPGA clock resource that you are using to clock the single-cycle timed loop that is accessing the read-side interface.
Note All memory interface signals must be used in a single-cycle timed loop. The clocks of this single-cycle timed loop must be specified as input clocks in the FPGA Base Clock Properties Dialog.
Note You must disable all synchronization registers for all DRAM FPGA I/O signals (by setting the value to 0). The DRAM interface signals are synchronous to the DRAM interface clock. Synchronization registers will cause a delay in sending and receiving data/commands to/from the DRAM interface, which can prevent proper operation. Always disable synchronization registers for synchronous interfaces where proper operation depends on no latency. For more information on disabling synchronization registers, refer to the Advanced Code Generation Page.
Note Depending on clock rates and your application, it may take several clock cycles for data input to the FIFO to be read from the FIFO.

The FIFO - 128 Bit memory interface is designed to simultaneously and continuously read and write data at speeds up to 40 MHz. It is possible to access the interface at up to 200 MHz, however, at speeds greater than 40 MHz, the Full and Data_Available signals may temporarily become TRUE and FALSE, respectively (stalling access to the FIFO).

DRAM Examples

LabVIEW contains example VIs that read and write to the FIFO memory interface for FlexRIO devices and other devices. The main interface for the PXIe-5641R is similar to the interface found on the FlexRIO devices. To access the Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO. The PXIe-5641R and the FlexRIO interfaces differ in terms of the bit widths of the interface and the maximum clock rate.