The Configuration instrument design library provides functionality to configure hardware settings and to check if the hardware is operating correctly.

PXIe-5624 FPGA

This library provides FPGA registers to access all the hardware subsystems of the PXIe-5624. This instrument design library contains FPGA VIs.

Open and Close Session

To configure the IF digitizer, you must open a configuration session. After finishing all configuration, close the configuration session.

Clock Configuration

You must configure the ADC Clock and downstream components, including the ADC itself, before acquiring IF In data. Use the Configure ADC Clock VI to select an onboard or external ADC Clock source and to configure and enable the ADC. For an onboard ADC Clock source, you can also select a Reference Clock and lock the ADC Clock to the selected Reference Clock. After the ADC Clock is configured and locked, the ADC Clock and the Data Clock in the device FPGA are enabled. The Configure ADC Clock VI reads the current clock configuration from the device and has no effect on the hardware configuration if the clock is already configured correctly and the clock PLLs are locked. The Initialize Clocks VI provides a faster alternative if you only want to configure the ADC Clock and Data Clock for an onboard source and are not yet ready to configure the ADC.

Digital Correction

Digital Correction VIs use calibration data from the Get Cal Data VI to select calibrated configurations for a specified frequency or power level. Use the Read Calibration Data VIs to read calibration data stored in the device. Use the Configure Calibrated IQ Correction host VI to apply calibration data at the configured center frequency.

Configure Dither

The Configure Dither VI enables a dither signal to the ADC and controls its power. Dither adds band-limited noise in the analog signal path to help reduce the quantization effects of the ADC and improve spectral performance.

Hardware Status

After configuring the IF or I/Q hardware, allow the hardware to settle prior to acquiring a signal. The Configuration instrument design library includes the general Check Status VI and more specific VIs to Read Device Status, Read Clock Status, Read Power, Read Temperature, and read or clear the input power protection status.

FPGA

The PXIe-5624 FPGA library includes the following sets of Registers VIs, which contain all the registers needed to configure the corresponding hardware:

  • Fixed Register VIs
  • System Register VIs
  • Digital Correction Register VIs
  • Compensate ADC Pipeline Register VIs

Connect the System Registers VI to the Instruction Framework to enable configuration of the device by the host VIs. Connect the Digital Correction VI to the I/Q signal to apply digital correction based on calibration data. To properly apply calibration IP to your application, you must include the Digital Correction VI, as shown in the IF digitizer sample projects.

Refer to the LabVIEW context help for detailed information about how to use the Configuration instrument design library VIs. You also can refer to the IF digitizer sample projects in LabVIEW to see how VIs in this library are used.