Instruction Framework

Use the Instruction Framework instrument design library to send register read and write instructions from your application on the host to the FPGA. Other instrument design libraries on the FPGA can define sets of registers used by that library and can accept read and write instructions for those registers from the host through the Instruction Framework library. When compared to using the FPGA Interface VIs to read and write controls and indicators on the top-level FPGA VI, the Instruction Framework library provides a more portable and flexible way to define and access FPGA registers in other instrument design libraries. With the Instruction Framework library, you can define and access registers that are not on the top-level FPGA VI. By using DMA to transfer data, the Instruction Framework library provides a significant performance benefit when you need to quickly issue a large number of register writes.

A single instance of the Instruction Framework can send register instructions to multiple instrument design libraries on the FPGA. Each instrument design library connected to the Instruction Framework instance receives all register instructions from the Instruction Framework but only processes the register instructions for the registers it has defined.

You can use multiple instances of this instrument design library in your FPGA application. Using multiple instances of the Instruction Framework is useful in applications where independent components each send register instructions to the FPGA because each Instruction Framework instance has a separate DMA FIFO for data transfer. Different instances of the Instruction Framework can send register instructions to the same instrument design library on the FPGA. Using the Instruction Framework library, you can arbitrate among register instructions with the same destination and then route a completed read instruction to the instance of the Instruction Framework that issued it.

This instrument design library includes host VIs and FPGA VIs. For each instance of the Instruction Framework, the host writes register instructions into a Host to Target DMA FIFO. The FPGA reads a register instruction from the DMA FIFO, decodes it, and sends it to all other instrument design libraries connected to that instance of the Instruction Framework. The FPGA waits for the current register instruction to be processed before decoding and sending the next register instruction.

Refer to the LabVIEW context help of the Instruction Framework LabVIEW VIs for more detailed information about the library interface.