Transceiver Lane and Quad Mapping
- Updated2025-04-01
- 1 minute(s) read
If your application requires multiple lanes, refer to the following tables for information about transceiver and RefClk selection when using the Xilinx tools to generate protocol IP.
| Connector | Lane | Quad Location | Physical Resource |
|---|---|---|---|
| PORT 0 | 0 | Quad 0 (Q0) | GTX_X0Y5 |
| 1 | GTX_X0Y4 | ||
| 2 | GTX_X0Y6 | ||
| 3 | GTX_X0Y7 | ||
| PORT 1 | 0 | Quad 1 (Q1) | GTX_X0Y9 |
| 1 | GTX_X0Y8 | ||
| 2 | GTX_X0Y10 | ||
| 3 | GTX_X0Y11 | ||
| PORT 2 | 0 | Quad 2 (Q2) | GTX_X0Y13 |
| 1 | GTX_X0Y12 | ||
| 2 | GTX_X0Y14 | ||
| 3 | GTX_X0Y15 | ||
| PORT 3 | 0 | Quad 3 (Q3) | GTX_X0Y17 |
| 1 | GTX_X0Y16 | ||
| 2 | GTX_X0Y18 | ||
| 3 | GTX_X0Y19 | ||
| PORT 4 | 0 | Quad 4 (Q4) | GTX_X0Y21 |
| 1 | GTX_X0Y20 | ||
| 2 | GTX_X0Y22 | ||
| 3 | GTX_X0Y23 | ||
| PORT 5 | 0 | Quad 5 (Q5) | GTX_X0Y25 |
| 1 | GTX_X0Y24 | ||
| 2 | GTX_X0Y26 | ||
| 3 | GTX_X0Y27 |
| Clock Signal | Quad Location | Physical Resource |
|---|---|---|
| MGT_RefClk2 | Quad 1 (Q1) | REFCLK1_Q1 |
| MGT_RefClk3 | Quad 3 (Q3) | REFCLK1_Q3 |
| MGT_RefClk4 | Quad 5 (Q5) | REFCLK1_Q5 |
For more information about lane and channel bonding caveats, including cases where you need to use single or multiple reference clocks for single or multiple transceivers, refer to 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) at xilinx.com.