If your application requires multiple lanes, refer to Table 1 and Table 2 for information about transceiver and RefClk selection when using the Xilinx tools to generate protocol IP.

Table 16. Transceiver Lane and Quad Mapping
Connector Lane Quad Location Physical Resource
PORT 0 0 Quad 3 (Q3) GTX_X0Y15
PORT 1 0 GTX_X0Y13
PORT 2 0 Quad 2 (Q2) GTX_X0Y10
PORT 3 0 GTX_X0Y8
Table 17. Clock Signal and Quad Mapping
Clock Signal Quad Location Physical Resource
MGT_RefClk0 Quad 3 (Q3) REFCLK1_Q3
MGT_RefClk1 Quad 2 (Q2) REFCLK0_Q2
MGT_RefClk2 Quad 3 (Q3) REFCLK0_Q3

For more information about lane and channel bonding caveats, including cases where you need to use single or multiple reference clocks for single or multiple transceivers, refer to 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) at xilinx.com.