Socketed CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI. Socketed CLIP also allows the CLIP to communicate directly with circuitry external to the FPGA.

The following sections provide information about how to configure your device for use with socketed CLIP.

PXIe-7902 Socketed CLIP

Refer to the following diagram for an overview of the PXIe-7902 socketed CLIP interface.

Figure 14. PXIe-7902 Socketed CLIP Diagram

The following signals are provided through the PXIe-7902 CLIP socket. You can use these signals to develop your own custom CLIP. For more information about how to configure the PXIe-7902 CLIP, refer to the NI High-Speed Serial Instruments Help.

Table 24. PXIe-7902 Socketed CLIP Signals
Port Direction Clock Domain Description
MGT_RefClk2_p In (pad) N/A Differential input clock that you must connect to an IBUFDS_
GTE2 input buffer primitive when this input clock is used in your design.
MGT_RefClk2_n In (pad) N/A
MGT_RefClk3_p In (pad) N/A Differential input clock that you must connect to an IBUFDS_
GTE2 input buffer primitive when this input clock is used in your design.
MGT_RefClk3_n In (pad) N/A
MGT_RefClk4_p In (pad) N/A Differential input clock that you must connect to an IBUFDS_
GTE2 input buffer primitive when this input clock is used in your design.
MGT_RefClk4_n In (pad) N/A
Port<0..5>_RX_p In (pad) N/A Dedicated MGT receive signals for Port <0..5>.
Port<0..5>_RX_n In (pad) N/A
Port<0..5>_TX_p Out (pad) N/A Dedicated MGT transmit signals for Port <0..5>.
Port<0..5>_TX_n Out (pad) N/A
GtxRxPolarity_in In (pad) 24-bit signal that indicates the polarity of the receive signal.

Some MGT signals have inverted polarity external to the FPGA; use this signal to determine which channels, if any, are inverted.
GtxTxPolarity_in In (pad) 24-bit signal that indicates the polarity of the transmit signal.

Some MGT signals have inverted polarity external to the FPGA; use this signal to determine which channels, if any, are inverted.
SocketClk40 In Clock A 40 MHz clock that runs continuously regardless of connectivity. This signal is connected to the 40 MHz Onboard Clock signal, which is the default top-level clock for the LabVIEW FPGA VI.
Port<0..5>_SCL In/Out Async Bidirectional serial clock signal for the two wire communication interface on the Port<0..5> connector.

Valid values are 0 and Z (open drain).

This signal is also called MODDEF1.

This signal has a 10 kOhm pull up to +3.3V.

You must assert aPort<_EnablePower to enable the Port<0..5>_SCL and Port<0..5>_SDA interface.
Port<0..5>_SDA In/Out Async Bidirectional serial data signal for the two wire communication interface on the Port<0..3> connector.

Valid values are 0 and Z (open drain).

This signal is also called MODDEF2.

This signal has a 10 kOhm pull up to +3.3V.

You must assert aPort_EnablePower to enable the Port<0..5>_SCL and Port<0..5>_SDA interface.
Port<0..5>_ModPrs_n In (pad) Indicates the presence of a device on the other end of the cable for each port.
MGT_RefClks_
ExtPllLocked In Async Indicates the state of the PLL within the clocking logic and provides the Reference Clock to the FPGA MGTs (MGT_
RefClkx signals).

Use this signal with MGT_
RefClks_Valid to gate and/or reset the clocking signals into any CLIP that depends on the MGT_RefClkx signals.
MGT_RefClks_
Valid In Async Indicates if the selected clock input to the clocking logic is valid and the PLL within the clocking logic has locked.

Use this signal to gate and/or reset the clocking signals into any CLIP that depends on the MGT_RefClkx signals.

On the rising edge of MGT_
RefClks_Valid, you may need to reset or relock state machines and/or internal PLLs sensitive to MGT_RefClkx signals.
DebugClks(5:0) Out Clock Debug ports to aid in debugging the clocking connections in the CLIP. These ports connect to frequency counters that can monitor the frequency of any clock that you connect to these ports.

Refer to the Debugging Link Connections Using Eye Scan section of ChapterDeveloping Applications for the High-Speed Serial Device, Developing Applications for the High-Speed Serial Device, for details about how to use these signals.
ExportedUser
ReferenceClk Out Clock Reserved for future use.
sFrontEnd
ConfigurationDone In SocketClk40 Asserts high and stays high when the power-on self-configuration (POSC) state machine is finished with configuration.

After the aResetSl signal transitions from high to low, indicating that the CLIP logic should come out of reset, a POSC reconfiguration occurs unconditionally.

The required clocking signals are not valid until after this signal asserts high.
sFrontEnd
ConfigurationPrepare In SocketClk40 Reserved for future use. NI recommends assigning this signal to sFront
EndConfigurationReady.
sFrontEnd
ConfigurationReady Out SocketClk40 Reserved for future use. NI recommends assigning this signal to sFront
EndConfigurationPrepare.
aPort_Enable
Power Out SocketClk40 Enables or disables the power supply on Port <0..5>.

Assert this signal to enable the power supply for its corresponding port.

You can leave this signal disabled when using copper cables. This signal is required when using optical cables.
aPort_Power
Good In SocketClk40 Indicates that the power supply for Port <0..5> is enabled.

This signal may deassert if an over-power condition occurs.
aOptical_Enable
Power Out SocketClk40 Enables or disables the optical power supply on Port <0..5>.

Assert this signal to enable the optical supply for its corresponding port.
aOptical_Power
Good In SocketClk40 Indicates that the optical power supply for Port <0..5> is enabled.

This signal may deassert if an over-power condition occurs.