The Frequency Counter is a module inside the FPGA that provides a built-in method for debugging clock signals during CLIP development. To use the Frequency Counter, complete the following steps:

  1. Attach clocks to one of the four DebugClk(3..0) signals in the CLIP.
  2. On the host, use the method provided on all high-speed serial device FPGA reference wires.

    The Read FPGA Frequency Counter method initiates a Frequency Counter measurement for 1 ms and reports the frequency of the selected clock. If the Frequency Counter cannot detect a clock signal, it returns Valid? as false. Valid frequencies are reliable between 2 kHz and 333.33 MHz.