Complete the following steps to configure your high-speed serial device LabVIEW project:

  1. Create a new project by selecting File » New » Project, or open an existing project by selecting File » Open.
  2. Right-click My Computer in the Project Explorer window and select New » Targets and Devices from the shortcut menu to display the Add Targets and Devices dialog box.
  3. Select New target or device and select your device.
  4. Add the protocol IP through your CLIP. Right-click the device name and select Properties » Component-Level IP.
    Note If you are using example CLIP or pre-made CLIP, you can import the CLIP using the dialog box, or you can click on the Create File icon to create a new CLIP using the CLIP Wizard.
    Note You can modify a CLIP by selecting the preexisting CLIP Declaration Name and clicking Modify File.
  5. If you are generating new CLIP, follow the instructions in the CLIP Wizard to interface your CLIP with LabVIEW FPGA. You do not need to use the CLIP Wizard if you are reusing an existing CLIP. Refer to the FPGA Module Help for more detailed information about the CLIP Wizard. The CLIP Wizard guides you through the following tasks.
    • Adding VHDL source, XDC constraints, and EDF/EDN/EDIF netlists
    • Configuring device types
    • Configuring generics
    • Performing syntax checks
    • Specifying how to use the signals in your CLIP
      Note In Step 2 of the CLIP Wizard, select the appropriate Component Level IP Type for your target.
      Note After you create the CLIP and add the files, you do not need to modify the CLIP for any changes to take place if you do not change the source paths. If you change the source paths or modify the CLIP source files, you must use the CLIP Wizard.
  6. Instantiate the CLIP in the I/O socket. When you add a new target to the project, LabVIEW automatically creates a compatible I/O socket in the project. Right-click the socket and select Properties, then select General under Category.
  7. Select a declaration from the drop-down menu under Socketed Component Level IP Declaration.
  8. Click OK. The user-defined signals in your CLIP appear under the socket item.
  9. Right-click the IO socket and select Properties » Clocking and IO to configure the Clocking and IO Configuration properties for your device.
    Note Clocking and routing information is compile-time static and cannot be reconfigured at runtime.
    Note If you are using an example project or a Sample Project, the Clocking and IO Configuration tabs are already configured. If you create a new project, default values are configured, but you must review the settings and ensure that they are correct. If you insert a CLIP into the socket but do not configure the Clocking and IO page, an error is returned.
    Note The high-speed serial devices support empty sockets.
  10. Select the Clocking tab.
  11. Under Input Clock Configuration, select your input clock and its frequency in MHz. The input clock is sourced from one of the following locations:
    • Device backplane (PXIe_Clk100)
    • CLK IN connector on the front panel
    • 10 MHz Onboard Clock (PXIe-6592R only)
  12. Under Output Clock Configuration, select any output reference clocks you want to use and specify their frequencies in MHz. The output clocks that you select here are routed to your CLIP for use with your application.
    Note (PXIe-6591R only) When CLK IN/OUT is enabled as an output reference clock, it routes the specified frequency to the SMA connector.
    Note (PXIe-6592R only) When PFI 0/CLK OUT, PFI 1, PFI 2, and PFI 3 are enabled as output reference clocks, they route the specified frequency to the corresponding SMB connector.
    Note If you specify an invalid combination of input clock frequencies and output clock frequencies, an error message appears and the OK button is dimmed until you reconfigure the clocks to a valid frequency combination.
  13. Select the IO Configuration tab.
  14. Under Active Serial Lanes, select the checkbox for any serial lanes that you want configured for Transmit (TX) or Receive (RX). Select the All/None checkbox to select/deselect all serial lanes.
    Note Selecting the active serial lanes adds additional placement constraints to your project based on the lanes you select, so ensure that you select all lanes used in your project.
  15. Under GPIO Configuration, use the Voltage Family selector box to specify the voltage level used by the GPIO (Digital Data and Control on the PXIe-6591R, and PFI 0, PFI 1, PFI 2, and PFI 3 on the PXIe-6592R).

    Refer to Table 1 for a list of clocking and routing dependencies for the PXIe-6591R and PXIe-7902. Refer to Table 2 for a list of clocking and routing dependencies for the PXIe-6592R.

  16. Click OK.
    Table 25. PXIe-6591R and PXIe-7902 Clocking and Routing Dependencies
    Connector Valid Configurations
    CLK IN/OUT Input clock or output clock
    Table 26. PXIe-6592R Clocking and Routing Dependencies
    Connector/Clock Valid Configurations Notes
    PFI 0/CLK IN Input clock or output clock When enabled as output clocks, PFI 0/CLK IN/OUT, PFI 1/
CLK OUT, PFI 2/CLK OUT, and PFI 3/CLK OUT must share the same frequency.

    The output of any enabled PFIx line is 10 MHz when Enable CPRI Output Clock Configuration is enabled.

    If PFI 0/CLK IN/OUT is not configured as the input clock or enabled as an output clock, you can configure PFI 0/CLK IN/OUT for GPIO.
    PFI 1 Output clock When enabled as output clocks, PFI 0/CLK IN/OUT, PFI 1/
CLK OUT, PFI 2/CLK OUT, and PFI 3/CLK OUT must share the same frequency.

    The output of any enabled PFIx line is 10 MHz when Enable CPRI Output Clock Configuration is enabled.

    If PFI 1/CLK OUT, PFI 2/
CLK OUT, and PFI 3/CLK OUT are not configured as output clocks, you can use them individually for GPIO.
    PFI 2 Output clock
    PFI 3 Output clock
    MGT_RefClk0 and MGT_RefClk1 — When Enable CPRI Output Clock Configuration is enabled, the internal reference clock is set to 153.6 MHz. This imposes frequency restrictions on MGT_RefClk0 and MGTRefClk1. The output of any PFI lines is 10 MHz, phase-aligned with the 153.6 MHz clock.
    MGT_RefClk2 — This clock’s frequency is always 156.25 MHz.

    The following steps show an example of how to configure the PXIe-6592R for 140 MHz output on MGT_RefClk0 from a 100 MHz input clock on PFI0/CLK IN.

  17. Right-click the IO socket and select Properties » Clocking and IO.
  18. Under Input Clock Configuration, select PFI0/CLK IN and enter 100.
  19. Under Output Clock Configuration, select the checkbox next to MGT_RefClk0 to enable it.
  20. Enter 140 in the text box to the right of MGT_RefClk0.
  21. Click OK.
    Note By selecting an input clock and an output clock in this example, the MGT_RefClk0 is phase loop-locked to the incoming 100 MHz clock. Refer to ChapterPXIe-6591R Hardware Architecture, PXIe-6591R Hardware Architecture, for more information about PXIe-6591R clocking capabilities. Refer to ChapterPXIe-6592R Hardware Architecture, PXIe-6592R Hardware Architecture, for more information about PXIe-6592R clocking capabilities. Refer to ChapterPXIe-7902 Hardware Architecture, PXIe-7902 Hardware Architecture, for more information about PXIe-7902 clocking capabilities.