LabVIEW FPGA does not support Verilog source files in Component Level IP. However, you can generate EDIF netlists from any synthesized Verilog components in the IP you are using and instantiate the netlist in a VHDL wrapper.The following steps are an example of how to generate an EDIF netlist from the IP core:

  1. Open the example project for your IP core in Vivado.
  2. Set the appropriate top-level source file for which you plan to generate a netlist.
  3. Run synthesis.
  4. Open the Synthesized Design using one of the following methods.
    • Select Open Synthesized Design in the Synthesis Completed pop-up window.
    • Select the Design Run tab, then select Open Synthesized Design in the left hand pane.
  5. In the Tcl Console, enter write_edif <name of entity>.edf to create the netlist that you use when you import the IP core into your LabVIEW project. The netlist location is indicated by the Tcl Console window.
  6. The following figure shows the cells associated with the design in the Netlist window.
  7. To build .edf files for an associated cell, enter the following command:
write_edif -cell <name of cell> <file name>.edf
For example, to create an .edf for clock_module_i, enter the following command:
write_edif -cell clock_module_i
aurora_64b66b_clock_module.edf
    Note You may have to specify a longer path name depending on the location of the cell in your project. For example, clock_module_i may be located under 
aurora_64b66b_0_block_i/clock_module_i.
  8. Copy the netlist into your LabVIEW FPGA CLIP directory.
  9. Include your netlist in the list of synthesis files when running the CLIP Wizard.