Total throughput depends on the SCTL rate from the FPGA that is reading or writing the DMA channels. The data throughput is calculated by the following equation:

(Data Width × Samples per Cycle) × Number of DMA FIFOs × SCTL Clock Rate = Data Throughput

The total data throughput cannot exceed the maximum data specification for your module. Refer to the specifications document for your module for information about data throughput limits.

Some remote controlling PCs and PXI Express chassis have slot bandwidth restrictions that may limit the maximum throughput of your application. Refer to the controller and chassis specifications for more information.

The number of array elements fed into the DMA FIFO from the Host can limit the maximum throughput for your application. Use large array subsets and set your FIFO depths to be deep enough to sustain high throughput.

For more detailed information about using DMA, DMA best practices, and how to make design decisions on how to implement DMA in your application, refer to the Transferring Data Using Direct Memory Access topic in the LabVIEW FPGA Module User Manual.